Patents by Inventor Zhendong Hong
Zhendong Hong has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11967291Abstract: A display may have a pixel array such as a liquid crystal pixel array. The pixel array may be illuminated by a backlight unit that includes an array of light-emitting diodes (LEDs). The backlight unit may determine the type of content in the image data. The backlight unit may decide to prioritize either mitigating halo or mitigating clipping based on the type of content. The determination of the type of content in the image data may be used to determine the brightness values for the LEDs in the LED array. If the content is determined to be a first type of content, at least one given LED in the LED array may have a different brightness value than if the content is determined to be a second, different type of content. Classifying content in the image data may be useful in optimizing visible artifacts such as visible halo and clipping.Type: GrantFiled: June 2, 2023Date of Patent: April 23, 2024Assignee: Apple Inc.Inventors: Mohammad Tofighi, Meng Cao, Pierre-Yves Emelie, Duane M Petrovich, Shuo Han, Zhendong Hong, Tobias Jung, Marc Albrecht, Jiulong Shan, Wei H Yao
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Publication number: 20160181380Abstract: Embodiments provided herein describe systems and methods for forming semiconductor devices. A semiconductor substrate is provided. A source region and a drain region are formed on the semiconductor substrate. A gate electrode is formed between the source region and the drain region. A contact is formed above at least one of the source region and the drain region. The contact includes an insulating layer formed above the semiconductor substrate, an interface layer formed above the insulating layer, and a metallic layer formed above the interface layer. The interface layer is operable as a barrier between a material of the insulating layer and a material of the metallic layer, reduces the electrical resistance between the material of the insulating layer and the material of the metallic layer, or a combination thereof.Type: ApplicationFiled: December 19, 2014Publication date: June 23, 2016Inventors: Amol Joshi, Sean Barstow, Paul Besser, Ashish Bodke, Guillaume Bouche, Nobumichi Fuchigami, Zhendong Hong, Shaoming Koh, Albert Sanghyup Lee, Salil Mujumdar, Abhijit Pethe, Mark Victor Raymond
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Patent number: 9362283Abstract: An integrated circuit product includes an NMOS transistor having a gate structure that includes an NMOS gate insulation layer, a first NMOS metal layer positioned on the NMOS gate insulation layer, an NMOS metal silicide material positioned above the first NMOS metal layer, and a layer of a second metal material positioned above and in contact with the NMOS gate insulation layer, the first NMOS metal layer, and the NMOS metal silicide layer. The PMOS transistor has a gate structure that includes a PMOS gate insulation layer, a first PMOS metal layer positioned on the PMOS gate insulation layer, a PMOS metal silicide material positioned above the first PMOS metal layer, and a layer of the second metal material positioned above and in contact with the PMOS gate insulation layer, the first PMOS metal layer, and the PMOS metal silicide layer.Type: GrantFiled: July 7, 2015Date of Patent: June 7, 2016Assignee: GLOBALFOUNDRIES Inc.Inventors: Zhendong Hong, Susie Tzeng, Amol Joshi, Ashish Bodke, Divya Pisharoty, Usha Raghuram, Olov Karlsson, Kisik Choi, Salil Mujumdar, Paul R. Besser, Jinping Liu, Hoon Kim
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Publication number: 20160093711Abstract: Devices with lightly-doped semiconductor channels (e.g., FinFETs) need mid-gap (˜4.6-4.7 eV) work-function layers, preferably with low resistivity and a wide process window, in the gate stack. Tantalum carbide (TaC) has a mid-gap work function that is insensitive to thickness. TaC can be deposited with good adhesion on high-k materials or on optional metal-nitride cap layers. TaC can also serve as the fill metal, or it can be used with other fills such as tungsten (W) or aluminum (Al). The TaC may be sputtered from a TaC target, deposited by ALD or CVD using TaCl4 and TMA, or produced by methane treatment of deposited Ta. Al may be added to tune the threshold voltage.Type: ApplicationFiled: June 25, 2014Publication date: March 31, 2016Inventors: Zhendong Hong, Paul Besser, Kisik Choi, Amol Joshi, Olov Karlsson, Susie Tzeng
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Patent number: 9297775Abstract: Barrier layers, barrier stacks, and seed layers for small-scale interconnects (e.g., copper) are combinatorially screened using test structures sputtered or co-sputtered through apertures of varying size. Various characteristics (e.g., resistivity, crystalline morphology, surface roughness) related to conductivity, diffusion blocking, and adhesion are measured before and/or after annealing and compared to arrive at materials and process parameters for low diffusion with high conductivity through the interconnect. Example results show that some formulations of tantalum-titanium barriers may replace thicker tantalum/tantalum-nitride stacks, in some cases with a Cu—Mn seed layer between the Ta—Ti and copper.Type: GrantFiled: May 23, 2014Date of Patent: March 29, 2016Assignee: Intermolecular, Inc.Inventors: Edwin Adhiprakasha, Sean Barstow, Ashish Bodke, Zhendong Hong, Usha Raghuram, Karthik Ramani, Vivian Ryan, Jingang Su, Xunyuan Zhang
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Patent number: 9246096Abstract: Embodiments of the invention generally relate to nonvolatile memory devices and methods for manufacturing such memory devices. The methods for forming improved memory devices, such as a ReRAM cells, provide optimized, atomic layer deposition (ALD) processes for forming a metal oxide film stack which contains at least one hard metal oxide film (e.g., metal is completely oxidized or substantially oxidized) and at least one soft metal oxide film (e.g., metal is less oxidized than hard metal oxide). The soft metal oxide film is less electrically resistive than the hard metal oxide film since the soft metal oxide film is less oxidized or more metallic than the hard metal oxide film. In one example, the hard metal oxide film is formed by an ALD process utilizing ozone as the oxidizing agent while the soft metal oxide film is formed by another ALD process utilizing water vapor as the oxidizing agent.Type: GrantFiled: February 17, 2015Date of Patent: January 26, 2016Assignees: Intermolecular, Inc., Kabushiki Kaisha Toshiba, SanDisk 3D LLCInventors: Zhendong Hong, Vidyut Gopal, Imran Hashim, Randall J. Higuchi, Tim Minvielle, Hieu Pham, Takeshi Yamaguchi
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Publication number: 20150338362Abstract: Barrier layers, barrier stacks, and seed layers for small-scale interconnects (e.g., copper) are combinatorially screened using test structures sputtered or co-sputtered through apertures of varying size. Various characteristics (e.g., resistivity, crystalline morphology, surface roughness) related to conductivity, diffusion blocking, and adhesion are measured before and/or after annealing and compared to arrive at materials and process parameters for low diffusion with high conductivity through the interconnect. Example results show that some formulations of tantalum-titanium barriers may replace thicker tantalum/tantalum-nitride stacks, in some cases with a Cu—Mn seed layer between the Ta—Ti and copper.Type: ApplicationFiled: May 23, 2014Publication date: November 26, 2015Applicant: Intermolecular Inc.Inventors: Edwin Adhiprakasha, Sean Barstow, Ashish Bodke, Zhendong Hong, Usha Raghuram, Karthik Ramani, Vivian Ryan, Jingang Su, Xunyuan Zhang
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Publication number: 20150311206Abstract: An integrated circuit product includes an NMOS transistor having a gate structure that includes an NMOS gate insulation layer, a first NMOS metal layer positioned on the NMOS gate insulation layer, an NMOS metal silicide material positioned above the first NMOS metal layer, and a layer of a second metal material positioned above and in contact with the NMOS gate insulation layer, the first NMOS metal layer, and the NMOS metal silicide layer. The PMOS transistor has a gate structure that includes a PMOS gate insulation layer, a first PMOS metal layer positioned on the PMOS gate insulation layer, a PMOS metal silicide material positioned above the first PMOS metal layer, and a layer of the second metal material positioned above and in contact with the PMOS gate insulation layer, the first PMOS metal layer, and the PMOS metal silicide layer.Type: ApplicationFiled: July 7, 2015Publication date: October 29, 2015Inventors: Zhendong Hong, Susie Tzeng, Amol Joshi, Ashish Bodke, Divya Pisharoty, Usha Raghuram, Olov Karlsson, Kisik Choi, Salil Mujumdar, Paul R. Besser, Jinping Liu, Hoon Kim
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Patent number: 9105497Abstract: One method for forming replacement gate structures for NMOS and PMOS transistors includes performing an etching process to remove a sacrificial gate structure for the NMOS and PMOS transistors to thereby define NMOS and PMOS gate cavities, depositing a gate insulation layer in the gate cavities, depositing a first metal layer on the gate insulation layer in the gate cavities, performing at least one process operation to form (1) an NMOS metal silicide material above the first metal layer within the NMOS gate cavity, the NMOS metal silicide material having a first amount of atomic silicon, and (2) a PMOS metal silicide material above the first metal layer within the PMOS gate cavity, the PMOS metal silicide material having a second amount of atomic silicon, and wherein the first and second amounts of atomic silicon are different, and forming gate cap layers within the NMOS and PMOS gate cavities.Type: GrantFiled: September 4, 2013Date of Patent: August 11, 2015Assignee: GLOBALFOUNDRIES Inc.Inventors: Zhendong Hong, Susie Tzeng, Amol Joshi, Ashish Bodke, Divya Pisharoty, Usha Raghuram, Olov Karlsson, Kisik Choi, Salil Mujumdar, Paul R. Besser, Jinping Liu, Hoon Kim
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Publication number: 20150179935Abstract: Embodiments of the invention generally relate to nonvolatile memory devices and methods for manufacturing such memory devices. The methods for forming improved memory devices, such as a ReRAM cells, provide optimized, atomic layer deposition (ALD) processes for forming a metal oxide film stack which contains at least one hard metal oxide film (e.g., metal is completely oxidized or substantially oxidized) and at least one soft metal oxide film (e.g., metal is less oxidized than hard metal oxide). The soft metal oxide film is less electrically resistive than the hard metal oxide film since the soft metal oxide film is less oxidized or more metallic than the hard metal oxide film. In one example, the hard metal oxide film is formed by an ALD process utilizing ozone as the oxidizing agent while the soft metal oxide film is formed by another ALD process utilizing water vapor as the oxidizing agent.Type: ApplicationFiled: February 17, 2015Publication date: June 25, 2015Inventors: Zhendong Hong, Vidyut Gopal, Imran Hashim, Randall J. Higuchi, Tim Minvielle, Hieu Pham, Takeshi Yamaguchi
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Patent number: 9059156Abstract: Methods to form metal gate transistor devices are disclosed. Erbium silicide layers can be used in CMOS transistors in which the work function of the erbium silicide layers can be tuned for use in PMOS and NMOS devices. A nanolaminate sputtering approach can be used in which silicon and erbium layers are alternatingly deposited to determine optimum layer properties, composition profiles, and erbium to silicon ratios for a particular gate stack.Type: GrantFiled: November 26, 2013Date of Patent: June 16, 2015Assignee: Intermolecular, Inc.Inventors: Zhendong Hong, Ashish Bodke, Olov Karlsson
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Patent number: 9006026Abstract: Embodiments of the invention generally relate to nonvolatile memory devices and methods for manufacturing such memory devices. The methods for forming improved memory devices, such as a ReRAM cells, provide optimized, atomic layer deposition (ALD) processes for forming a metal oxide film stack which contains at least one hard metal oxide film (e.g., metal is completely oxidized or substantially oxidized) and at least one soft metal oxide film (e.g., metal is less oxidized than hard metal oxide). The soft metal oxide film is less electrically resistive than the hard metal oxide film since the soft metal oxide film is less oxidized or more metallic than the hard metal oxide film. In one example, the hard metal oxide film is formed by an ALD process utilizing ozone as the oxidizing agent while the soft metal oxide film is formed by another ALD process utilizing water vapor as the oxidizing agent.Type: GrantFiled: August 22, 2014Date of Patent: April 14, 2015Assignees: Intermolecular, Inc., Kabushiki Kaisha Toshiba, SanDisk 3D LLCInventors: Zhendong Hong, Vidyut Gopal, Imran Hashim, Randall J. Higuchi, Tim Minvielle, Hieu Pham, Takeshi Yamaguchi
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Publication number: 20150091105Abstract: Erbium silicide layers can be used in CMOS transistors in which the work function of the erbium silicide layers can be tuned for use in PMOS and NMOS devices. A nano-laminate sputtering approach can be used in which silicon and erbium layers are alternatingly deposited to determine optimum layer properties, composition profiles, and erbium to silicon ratios for a particular gate stack.Type: ApplicationFiled: November 26, 2013Publication date: April 2, 2015Applicant: Intermolecular Inc.Inventors: Zhendong Hong, Ashish Bodke, Olov Karlsson
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Publication number: 20150061027Abstract: One method for forming replacement gate structures for NMOS and PMOS transistors includes performing an etching process to remove a sacrificial gate structure for the NMOS and PMOS transistors to thereby define NMOS and PMOS gate cavities, depositing a gate insulation layer in the gate cavities, depositing a first metal layer on the gate insulation layer in the gate cavities, performing at least one process operation to form (1) an NMOS metal silicide material above the first metal layer within the NMOS gate cavity, the NMOS metal silicide material having a first amount of atomic silicon, and (2) a PMOS metal silicide material above the first metal layer within the PMOS gate cavity, the PMOS metal silicide material having a second amount of atomic silicon, and wherein the first and second amounts of atomic silicon are different, and forming gate cap layers within the NMOS and PMOS gate cavities.Type: ApplicationFiled: September 4, 2013Publication date: March 5, 2015Applicant: GLOBALFOUNDRIES Inc.Inventors: Zhendong Hong, Susie Tzeng, Amol Joshi, Ashish Bodke, Divya Pisharoty, Usha Raghuram, Olov Karlsson, Kisik Choi, Salil Mujumdar, Paul R. Besser, Jinping Liu, Hoon Kim
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Publication number: 20150025670Abstract: Substrate processing including correction for deposition location is described, including a combinatorial processing chamber that incorporates the correction. The combinatorial processing chamber can be used to process multiple regions of a substrate using different processing parameters on different regions. For example, one region can have one material deposited on it and another region can have a different material deposited on it, although other combinations and variations are possible. The combinatorial processing chamber uses a rotating and revolving substrate pedestal to be able to deposit on all locations or positions on a substrate. The combinatorial processing chamber uses a correction factor that accounts for variations in alignment and/or configuration of the processing chamber so that the actual location of deposition of a region is approximately the same as a desired location of deposition.Type: ApplicationFiled: October 2, 2014Publication date: January 22, 2015Inventors: Jeremy Cheng, Indranil De, Ho Yin Owen Fong, Zhendong Hong, Dan Wang
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Patent number: 8920618Abstract: Apparatuses and methods for high-deposition-rate sputtering for depositing layers onto a substrate are disclosed. The apparatuses generally comprise a process chamber; one or more sputtering sources disposed within the process chamber, wherein each sputtering source comprises a sputtering target; a substrate support disposed within the process chamber; a shield positioned between the sputtering sources and the substrate, the shield comprising an aperture positioned under each sputtering source; and a transport system connected to the substrate support capable of positioning the substrate such that one of a plurality of site-isolated regions on the substrate can be exposed to sputtered material through the aperture positioned under each of the sputtering sources; wherein the spacing between the sputtering target and the substrate is less than 100 mm. The apparatus enables high deposition rate sputtering onto site-isolated regions on the substrate.Type: GrantFiled: December 29, 2011Date of Patent: December 30, 2014Assignee: Intermolecular, Inc.Inventors: Hong Sheng Yang, Zhendong Hong, Chi-I Lang
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Publication number: 20140363942Abstract: Tungsten silicide layers can be used in CMOS transistors in which the work function of the tungsten silicide layers can be tuned for use in PMOS and NMOS devices. A co-sputtering approach can be used in which silicon and tungsten are deposited on a high dielectric constant gate dielectric layer. The tungsten silicide layer can be annealed at or above a critical temperature to optimize the resistivity of the tungsten silicide layer. In some embodiments, the concentration of as-deposited tungsten silicide can be between 50 at % silicon to 80 at % silicon. The critical temperatures can be lower at higher silicon concentration, such as 700 C. at 63 at % silicon to 600 C. at 74 at % silicon.Type: ApplicationFiled: June 11, 2013Publication date: December 11, 2014Inventors: Zhendong Hong, Ashish Bodke, Susie Tzeng
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Publication number: 20140363920Abstract: Embodiments of the invention generally relate to nonvolatile memory devices and methods for manufacturing such memory devices. The methods for forming improved memory devices, such as a ReRAM cells, provide optimized, atomic layer deposition (ALD) processes for forming a metal oxide film stack which contains at least one hard metal oxide film (e.g., metal is completely oxidized or substantially oxidized) and at least one soft metal oxide film (e.g., metal is less oxidized than hard metal oxide). The soft metal oxide film is less electrically resistive than the hard metal oxide film since the soft metal oxide film is less oxidized or more metallic than the hard metal oxide film. In one example, the hard metal oxide film is formed by an ALD process utilizing ozone as the oxidizing agent while the soft metal oxide film is formed by another ALD process utilizing water vapor as the oxidizing agent.Type: ApplicationFiled: August 22, 2014Publication date: December 11, 2014Inventors: Zhendong Hong, Vidyut Gopal, Imran Hashim, Randall J. Higuchi, Tim Minvielle, Hieu Pham, Takeshi Yamaguchi
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Patent number: 8882917Abstract: Substrate processing including correction for deposition location is described, including a combinatorial processing chamber that incorporates the correction. The combinatorial processing chamber can be used to process multiple regions of a substrate using different processing parameters on different regions. For example, one region can have one material deposited on it and another region can have a different material deposited on it, although other combinations and variations are possible. The combinatorial processing chamber uses a rotating and revolving substrate pedestal to be able to deposit on all locations or positions on a substrate. The combinatorial processing chamber uses a correction factor that accounts for variations in alignment and/or configuration of the processing chamber so that the actual location of deposition of a region is approximately the same as a desired location of deposition.Type: GrantFiled: December 31, 2009Date of Patent: November 11, 2014Assignee: Intermolecular, Inc.Inventors: Jeremy Cheng, Ho Yin Owen Fong, Dan Wang, Zhendong Hong, Indranil De
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Patent number: 8854067Abstract: Methods and structures are described for determining contact resistivities and Schottky barrier heights for conductors deposited on semiconductor wafers that can be combined with combinatorial processing, allowing thereby numerous processing conditions and materials to be tested concurrently. Methods for using multi-ring as well as single-ring CTLM structures to cancel parasitic resistance are also described, as well as structures and processes for inline monitoring of properties.Type: GrantFiled: August 24, 2012Date of Patent: October 7, 2014Assignees: Intermolecular, Inc., GLOBALFOUNDRIES, Inc.Inventors: Amol Joshi, Charlene Chen, John Foster, Zhendong Hong, Olov Karlsson, Bei Li, Dipankar Pramanik, Usha Raghuram, Mark Victor Raymond, Jingang Su, Bin Yang