Abstract: A display device, a gate driving circuit and a gate driving unit are provided. The gate driving unit includes: a signal maintenance circuit configured to, in the case that a first clock signal at a high level is received, output a high level in accordance with an inputted trigger signal at a high level; a first-level output circuit configured to, in the case that a second clock signal at a high level is received, output a first-level driving signal at a high level in accordance with the high level from an output end of the signal maintenance circuit; and a second-level output circuit configured to, in the case that a third clock signal at a high level is received, output a second-level driving signal at a high level in accordance with the high level from an output end of the first-level output circuit.

Abstract: The present disclosure provides an array substrate, a manufacturing method thereof and a display device. The array substrate comprises a base substrate; a signal line and an electrode arranged in different layers on the base substrate, and an insulating layer located between the signal line and the electrode. The array substrate further comprises a dielectric film located between the signal line and the insulating layer, the dielectric film covering the signal line; and/or a dielectric film located between the electrode and the insulating layer, the dielectric film covering the electrode.

Abstract: The present disclosure relates to a display substrate comprising a substrate; a data line disposed over the substrate; a first insulating layer disposed on the data line; a second insulating layer disposed on the first insulating layer; a first transparent electrode disposed on the second insulating layer. The present disclosure further relates to a manufacturing method of a display substrate and a display device.

Abstract: The present disclosure relates to an array substrate, a method of manufacturing the same and a display device. The array substrate comprises a gate line PAD region and a data line PAD region. In the gate line PAD region of the array substrate, gate-line wirings, which are parallel to the gate lines and are electrically insulated from the gate lines, are provided between adjacent gate lines. In the data line PAD region of the array substrate, data-line wirings, which are parallel to the data lines and are electrically insulated from the data lines, are provided between adjacent data lines. Both of the gate-line wirings and the data-line wirings are conductive wiring segments. By forming the gate-line wirings and the data-line wirings in the PAD region, the ability of resisting scratch of the product can be improved while not deteriorating performance of display of the product.

Abstract: The present disclosure relates to an array substrate, a method of manufacturing the same and a display device. The array substrate comprises a gate line PAD region and a data line PAD region. In the gate line PAD region of the array substrate, gate-line wirings, which are parallel to the gate lines and are electrically insulated from the gate lines, are provided between adjacent gate lines. In the data line PAD region of the array substrate, data-line wirings, which are parallel to the data lines and are electrically insulated from the data lines, are provided between adjacent data lines. Both of the gate-line wirings and the data-line wirings are conductive wiring segments. By forming the gate-line wirings and the data-line wirings in the PAD region, the ability of resisting scratch of the product can be improved while not deteriorating performance of display of the product.

Abstract: A method for producing an array substrate is provided. The method includes: forming metal film layers and patterning the metal film layers to form a plurality rows of gate lines and a plurality columns of data lines crossed to each other in the non-display area and forming thin film transistors; forming a pad part at one end of the gate lines or data lines. The process of producing the pad part includes: forming a first insulation layer on the metal film layers by patterning; forming an etching protection layer, a source and drain metal layer and a second insulation layer sequentially by patterning, wherein the first insulation layer, the etching protection layer, the source and drain metal layer and the second insulation layer form a trapezoid stack.

Abstract: The present disclosure discloses an array substrate including a display area and a data lead area. The display area includes data signal lines and gate lines. The data lead area includes peripheral wirings connecting the data signal lines and wiring terminals. The peripheral wirings include a plurality of metal traces which are corresponding to the data signal lines in a one-to-one manner and manufactured from a same layer as the gate lines. Each of the metal traces is connected to one of the data signal lines which is corresponding to the each of the metal trace.

Abstract: The present application discloses a display substrate comprising a base substrate; a first electrode on the base substrate; a first insulating layer on a side of the first electrode distal to the base substrate; a thin film transistor on a side of the first insulating layer distal to the first electrode; a second insulating layer on a side of the thin film transistor distal to the first insulating layer; an organic layer on a side of the second insulating layer distal to the thin film transistor; and a second electrode on a side of the organic layer distal to the second insulating layer.

Abstract: The present disclosure provides an array substrate, a manufacturing method thereof and a display device. The array substrate comprises a base substrate; a signal line and an electrode arranged in different layers on the base substrate, and an insulating layer located between the signal line and the electrode. The array substrate further comprises a dielectric film located between the signal line and the insulating layer, the dielectric film covering the signal line; and/or a dielectric film located between the electrode and the insulating layer, the dielectric film covering the electrode.

Abstract: An array substrate is disclosed, which includes a connection structure of a second short-circuit ring and one corresponding data line, and this connection structure includes: a first electrode disposed on a base substrate; a connection line disposed on the first electrode; a first insulating layer disposed on the first electrode and the connection line, in which the data line connected with the second short-circuit ring is disposed on the first insulating layer; a second insulating layer disposed on the data line connected with the second short-circuit ring; and a second electrode disposed on the second insulating layer, in which the second electrode is connected with the data line connected with the second short-circuit ring through a first via hole and connected with the first electrode through a second via hole.

Abstract: An array substrate comprises a plurality of data lines and a plurality of gate lines arranged to intersect with each other, an annular common signal line surrounding the data lines and the gate lines, and at least one annular repair line. The repair line is electrically connected with the common signal line through an anti-static ring. The repair line comprises a first line segment and a second line segment insulated from each other. The first line segment intersects with and is insulated from each of the data lines, the second line segment does not intersect with the data lines and is electrically connected with the common signal line through the anti-static ring. A repair portion is arranged between the first line segment and the second line segment, which is used for enabling the first line segment to be electrically connected with the second line segment after being welded.

Abstract: An array substrate, a manufacture method thereof and a display device are provided. The array substrate includes: gate lines and data lines which are crossed to define a plurality of pixel units; and common electrode lines intersected with the data lines, the pixel units being provided with pixel electrodes; wherein, the common electrode lines are provided with first protrusions electrically connected to the common electrode lines; the gate lines are provided with first grooves; the first protrusions are disposed in the first grooves; and the pixel electrodes are overlapped with corresponding first protrusions.

Abstract: The present disclosure discloses a thin film transistor comprising: an active layer; an etching barrier layer arranged on the active layer and formed with a plurality of via holes therein; and a source electrode and a drain electrode arranged on the etching barrier layer, wherein the source electrode comprises at least two sub source electrodes and the drain electrode comprises at least two sub drain electrodes; and the sub source electrodes and the sub drain electrodes constitute at least two parallel sub-switches, each of which comprises a sub source electrode and a sub drain electrode, and the sub source electrode and the sub drain electrode are electrically connected to the active layer through the via holes in the etching barrier layer, respectively. The present disclosure further discloses a method of manufacturing a thin film transistor, an array substrate and a display apparatus.

Abstract: The present invention relates to the technical field of display, and in particular to a post spacer, a display panel and a display device. The post spacer includes a support post and a support pillow, wherein the support pillow is formed of a plurality of sub-pillows dispersedly arranged below the bottom of the support post. Since the post spacer is provided with the support pillows dispersedly arranged below the bottom of the support post, the bottom of the support post can be more uniformly stressed, and the support pillow can further provide a certain antiskid effect. Therefore, the post spacer of the present invention has a better supporting effect and can effectively avoid Mura faults.

Abstract: The present disclosure provides a display substrate, its testing method and its manufacturing method. A first testing terminal is connected to a gate electrode of a first TFT, a second testing terminal is connected to a source electrode of the first TFT and a drain electrode of a second TFT, a third testing terminal is connected to a gate electrode of the second TFT, and a fourth testing terminal is connected to a drain electrode of the first TFT and a source electrode of the second TFT.

Abstract: A detecting method and a detecting apparatus for detection of a gate line disconnection. The gate line disconnection detecting method includes step 1: providing a first unit (41) at least capable of receiving signals at one end of a gate line to be detected (2), and providing a second unit (42) at least capable of transmitting signals at the other end of it; step 2: providing a first signal receiving unit (51) for receiving signals on a gate line other than the gate line to be detected (2). With respect to the gate line disconnection detecting method, whether disconnection occurs or not is judged depending on the signal strength received by the first signal receiving unit (51), and thus, the case that in a gate line disconnection detection of a bilateral drive type display device, whether a gate line is disconnected or not can be accurately detected, is realized. By it, technical supports are provided for getting rid of bad products timely, and a goal of promoting the yield of products is achieved.

Abstract: Embodiments of the disclosure provide an array substrate and a manufacture method thereof. The array substrate comprises a display region and a non-display region, the display region comprises a transistor, the transistor comprises a source electrode, a drain electrode and an active layer, the source electrode and the drain electrode are provided on the active layer and are respectively provided at two ends of the active layer. The non-display region is provided with an alignment mark, the alignment mark is provided in a same layer as the active layer and is configured for aligning the source electrode and the drain electrode with the active layer in the case of re-fabricating the source electrode and the drain electrode.

Abstract: An array substrate, a manufacture method thereof and a display device are provided. The array substrate includes: gate lines and data lines which are crossed to define a plurality of pixel units; and common electrode lines intersected with the data lines, the pixel units being provided with pixel electrodes; wherein, the common electrode lines are provided with first protrusions electrically connected to the common electrode lines; the gate lines are provided with first grooves; the first protrusions are disposed in the first grooves; and the pixel electrodes are overlapped with corresponding first protrusions.

Abstract: An array substrate is disclosed, which includes a connection structure of a second short-circuit ring and one corresponding data line, and this connection structure includes: a first electrode disposed on a base substrate; a connection line disposed on the first electrode; a first insulating layer disposed on the first electrode and the connection line, in which the data line connected with the second short-circuit ring is disposed on the first insulating layer; a second insulating layer disposed on the data line connected with the second short-circuit ring; and a second electrode disposed on the second insulating layer, in which the second electrode is connected with the data line connected with the second short-circuit ring through a first via hole and connected with the first electrode through a second via hole.

Abstract: The present invention provides an arrayed substrate, a method for manufacturing the same and a display device. It relates to a field of display technology. The short-circuit defect between the lead wires may be avoided while reducing a spacing between the adjacent two lead lines in a limited space for wiring.