Patents by Inventor Zheng-Chang MU

Zheng-Chang MU has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240079485
    Abstract: A high electron mobility transistor device including a channel layer, a first barrier layer, and a P-type gallium nitride layer is provided. The first barrier layer is disposed on the channel layer. The P-type gallium nitride layer is disposed on the first barrier layer. The first thickness of the first barrier layer located directly under the P-type gallium nitride layer is greater than the second thickness of the first barrier layer located on two sides of the P-type gallium nitride layer.
    Type: Application
    Filed: October 27, 2022
    Publication date: March 7, 2024
    Applicant: Powerchip Semiconductor Manufacturing Corporation
    Inventors: Jih-Wen Chou, Chih-Hung Lu, Bo-An Tsai, Zheng-Chang Mu, Po-Hsien Yeh, Robin Christine Hwang
  • Patent number: 9741607
    Abstract: Semiconductor devices are provided having large vias, such as under bonding pads, to increase the via open area ratio, increase the via etching rate, and avoid inter-metal dielectric cracking and damage to the integrated circuit. The via is defined as a large open area in the inter-metal dielectric layer between an isolated conductive bottom substrate layer and a conductive top layer. Methods of manufacturing semiconductor devices with a large via are also provided.
    Type: Grant
    Filed: November 15, 2016
    Date of Patent: August 22, 2017
    Assignee: Macronix International Co., Ltd.
    Inventors: Zheng-Chang Mu, Cheng-Wei Lin, Kuang-Wen Liu
  • Publication number: 20170062270
    Abstract: Semiconductor devices are provided having large vias, such as under bonding pads, to increase the via open area ratio, increase the via etching rate, and avoid inter-metal dielectric cracking and damage to the integrated circuit. The via is defined as a large open area in the inter-metal dielectric layer between an isolated conductive bottom substrate layer and a conductive top layer. Methods of manufacturing semiconductor devices with a large via are also provided.
    Type: Application
    Filed: November 15, 2016
    Publication date: March 2, 2017
    Inventors: Zheng-Chang MU, Cheng-Wei LIN, Kuang-Wen LIU
  • Patent number: 9536808
    Abstract: Semiconductor devices are provided having large vias, such as under bonding pads, to increase the via open area ratio, increase the via etching rate, and avoid inter-metal dielectric cracking and damage to the integrated circuit. The via is defined as a large open area in the inter-metal dielectric layer between an isolated conductive bottom substrate layer and a conductive top layer. Methods of manufacturing semiconductor devices with a large via are also provided.
    Type: Grant
    Filed: June 16, 2015
    Date of Patent: January 3, 2017
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Zheng-Chang Mu, Cheng-Wei Lin, Kuang-Wen Liu
  • Publication number: 20160372401
    Abstract: Semiconductor devices are provided having large vias, such as under bonding pads, to increase the via open area ratio, increase the via etching rate, and avoid inter-metal dielectric cracking and damage to the integrated circuit. The via is defined as a large open area in the inter-metal dielectric layer between an isolated conductive bottom substrate layer and a conductive top layer. Methods of manufacturing semiconductor devices with a large via are also provided.
    Type: Application
    Filed: June 16, 2015
    Publication date: December 22, 2016
    Inventors: Zheng-Chang MU, Cheng-Wei LIN, Kuang-Wen LIU