Patents by Inventor Zheng-Jun Lin
Zheng-Jun Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11942150Abstract: A resistive random-access memory (RRAM) circuit includes an RRAM device configured to output a cell current responsive to a bit line voltage, and a current limiter including an input terminal coupled to the RRAM device, first and second parallel current paths configured to conduct the cell current between the input terminal and a reference voltage node, and an amplifier configured to generate a first signal responsive to a voltage level at the input terminal and a reference voltage level. Each of the first and second current paths includes a switching device configured to selectively conduct a portion of the cell current responsive to the first signal.Type: GrantFiled: November 10, 2022Date of Patent: March 26, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chung-Cheng Chou, Zheng-Jun Lin, Pei-Ling Tseng
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Publication number: 20240062815Abstract: A memory device includes a memory cell and a sense amplifier. The sense amplifier has a reference circuit configured to output a reference voltage and a sensing circuit connected to the memory cell. A comparator includes a first input and a second input, with the first input connected to the reference circuit to receive the reference voltage, and the second input connected to the memory cell.Type: ApplicationFiled: August 10, 2023Publication date: February 22, 2024Inventors: Zheng-Jun LIN, Chung-Cheng CHOU, Pei-Ling TSENG
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Publication number: 20240036597Abstract: A voltage regulator circuit is provided. The voltage regulator circuit includes a voltage regulator configured to provide an output voltage at an output terminal. A plurality of macros are connectable at a plurality of connection nodes of a connector connected to the output terminal of the voltage regulator. A feedback circuit having a plurality of feedback loops is connectable to the plurality of connection nodes. The feedback loop of the plurality of feedback loops, when connected to a connection node of the plurality of connection nodes, is configured to provide an instantaneous voltage of the connection node as a feedback to the voltage regulator. The voltage regulator is configured, in response to the instantaneous voltage, regulate the output voltage to maintain the instantaneous voltage of the connection node approximately equal to a reference voltage.Type: ApplicationFiled: July 29, 2022Publication date: February 1, 2024Inventors: Zheng-Jun Lin, Chung-Cheng Chou, Yu-Der Chih, Chin-I Su
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Patent number: 11837287Abstract: A memory device includes a memory cell and a sense amplifier. The sense amplifier has a reference circuit configured to output a reference voltage and a sensing circuit connected to the memory cell. A comparator includes a first input and a second input, with the first input connected to the reference circuit to receive the reference voltage, and the second input connected to the memory cell. A precharger is configured to selectively precharge the sensing circuit to a predetermined precharge voltage.Type: GrantFiled: May 26, 2022Date of Patent: December 5, 2023Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Zheng-Jun Lin, Chung-Cheng Chou, Pei-Ling Tseng
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Publication number: 20230377648Abstract: A method of operating a memory circuit includes generating a first current in response to a first voltage. The first current includes a first set of leakage currents and a first write current. The method further includes generating, by a tracking circuit, a second set of leakage currents configured to track the first set of leakage currents of the first column of memory cells, and mirroring the first current in a first path with a second current in a second path by a first current mirror. The second current includes the second set of leakage currents and a second write current. The first write current corresponds to the second write current. The first set of leakage currents corresponds to the second set of leakage currents.Type: ApplicationFiled: July 31, 2023Publication date: November 23, 2023Inventors: Chin-I SU, Chung-Cheng CHOU, Yu-Der CHIH, Zheng-Jun LIN
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Publication number: 20230335189Abstract: In some aspects of the present disclosure, a memory device is disclosed. In some aspects, the memory device includes a first voltage regulator to receive a word line voltage provided to a memory array; a resistor network coupled to the first voltage regulator to provide an inhibit voltage to the memory array, wherein the resistor network comprises a plurality of resistors and wherein each of the resistors are coupled in series to an adjacent one of the plurality of resistors; and a switch network comprising a plurality of switches, wherein each of the switches are coupled to a corresponding one of the plurality of resistors and to the memory array via a second voltage regulator.Type: ApplicationFiled: June 16, 2023Publication date: October 19, 2023Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Zheng-Jun Lin, Chin-I Su, Pei-Ling Tseng, Chung-Cheng Chou
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Patent number: 11735263Abstract: A method of operating a memory circuit includes generating a first voltage by a first amplifier circuit of a first driver circuit coupled to a first column of memory cells, and generating a first current in response to the first voltage. The first current includes a first set of leakage currents and a first write current. The method further includes generating, by a tracking circuit, a second set of leakage currents configured to track the first set of leakage currents of the first column of memory cells, and mirroring the first current in a first path with a second current in a second path by a first current mirror. The second current includes the second set of leakage currents and a second write current. The first write current corresponds to the second write current. The first set of leakage currents corresponds to the second set of leakage currents.Type: GrantFiled: July 22, 2022Date of Patent: August 22, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chin-I Su, Chung-Cheng Chou, Yu-Der Chih, Zheng-Jun Lin
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Publication number: 20230253041Abstract: A memory circuit includes a first driver circuit, a memory cell array including a first column of memory cells, a first transistor coupled between the first driver circuit and the memory cell array, a second driver circuit, a first column of tracking cells and a header circuit coupled to the first driver circuit and the second driver circuit. The first transistor is configured to receive a first select signal. The first column of tracking cells is configured to track a leakage current of the first column of memory cells, and is coupled between a first conductive line and a second conductive line, the first conductive line being coupled to the second driver circuit.Type: ApplicationFiled: April 20, 2023Publication date: August 10, 2023Inventors: Chin-I SU, Chung-Cheng CHOU, Yu-Der CHIH, Zheng-Jun LIN
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Patent number: 11715518Abstract: In some aspects of the present disclosure, a memory device is disclosed. In some aspects, the memory device includes a first voltage regulator to receive a word line voltage provided to a memory array; a resistor network coupled to the first voltage regulator to provide an inhibit voltage to the memory array, wherein the resistor network comprises a plurality of resistors and wherein each of the resistors are coupled in series to an adjacent one of the plurality of resistors; and a switch network comprising a plurality of switches, wherein each of the switches are coupled to a corresponding one of the plurality of resistors and to the memory array via a second voltage regulator.Type: GrantFiled: September 9, 2021Date of Patent: August 1, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Zheng-Jun Lin, Chin-I Su, Pei-Ling Tseng, Chung-Cheng Chou
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Publication number: 20230236929Abstract: A semiconductor device includes an error correction code circuit and a register circuit. The error correction code circuit is configured to generate first data according to second data. The register circuit is configured to generate reset information according to a difference between the first data and the second data, for adjusting a memory cell associated with the second data. A method is also disclosed herein.Type: ApplicationFiled: March 14, 2023Publication date: July 27, 2023Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Zheng-Jun LIN, Pei-Ling TSENG, Hsueh-Chih YANG, Chung-Cheng CHOU, Yu-Der CHIH
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Publication number: 20230207005Abstract: A memory device includes RRAM memory cells configured to form a zero-transistor and one-resistor (0T1R) array structure in which access transistors of the RRAM memory cells are bypassed or removed. Alternatively, the access transistors of the RRAM memory cells may be arranged in a parallel structure to reduce associated IR drop and thus enable reduced write voltage operation.Type: ApplicationFiled: May 31, 2022Publication date: June 29, 2023Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Zheng-Jun Lin, Chung-Cheng Chou, Yu-Der Chih
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Patent number: 11636896Abstract: A memory circuit includes a first driver circuit, a first column of memory cells coupled to the first driver circuit, a first current source, a tracking circuit configured to track a leakage current of the first column of memory cells, and a footer circuit coupled to the first column of memory cells, the first current source and the tracking circuit.Type: GrantFiled: November 24, 2020Date of Patent: April 25, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chin-I Su, Chung-Cheng Chou, Yu-Der Chih, Zheng-Jun Lin
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Patent number: 11609815Abstract: A semiconductor device includes a memory circuit, an error correction code circuit, a register circuit and a write circuit. The memory circuit is configured to output, in response to at least one address signal, first data associated with at least one memory cell in the memory circuit. The error correction code circuit is configured to convert the first data to second data and configured to generate error information when the first data is not identical to the second data. The register circuit is configured to output, based on the error information, reset information corresponding to the at least one address signal. The write circuit is configured to reset the at least one memory cell according to the reset information. A method is also disclosed herein.Type: GrantFiled: August 30, 2021Date of Patent: March 21, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Zheng-Jun Lin, Pei-Ling Tseng, Hsueh-Chih Yang, Chung-Cheng Chou, Yu-Der Chih
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Publication number: 20230072287Abstract: A resistive random-access memory (RRAM) circuit includes an RRAM device configured to output a cell current responsive to a bit line voltage, and a current limiter including an input terminal coupled to the RRAM device, first and second parallel current paths configured to conduct the cell current between the input terminal and a reference voltage node, and an amplifier configured to generate a first signal responsive to a voltage level at the input terminal and a reference voltage level. Each of the first and second current paths includes a switching device configured to selectively conduct a portion of the cell current responsive to the first signal.Type: ApplicationFiled: November 10, 2022Publication date: March 9, 2023Inventors: Chung-Cheng CHOU, Zheng-Jun LIN, Pei-Ling TSENG
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Publication number: 20230065104Abstract: The disclosed invention presents a self-tracking reference circuit that compensates for IR drops and achieves the target resistance state at different temperatures after write operations. The disclosed self-tracking reference circuit includes a replica access path, a configurable resistor network, a replica selector mini-array and a step current generator that track PVT variations to provide a PVT tracking level for RRAM verify operation.Type: ApplicationFiled: November 7, 2022Publication date: March 2, 2023Inventors: Zheng-Jun Lin, Chung-Cheng Chou, Yu-Der Chih, Pei-Ling Tseng
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Publication number: 20230063758Abstract: A semiconductor device includes a memory circuit, an error correction code circuit, a register circuit and a write circuit. The memory circuit is configured to output, in response to at least one address signal, first data associated with at least one memory cell in the memory circuit. The error correction code circuit is configured to convert the first data to second data and configured to generate error information when the first data is not identical to the second data. The register circuit is configured to output, based on the error information, reset information corresponding to the at least one address signal. The write circuit is configured to reset the at least one memory cell according to the reset information. A method is also disclosed herein.Type: ApplicationFiled: August 30, 2021Publication date: March 2, 2023Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Zheng-Jun LIN, Pei-Ling TSENG, Hsueh-Chih YANG, Chung-Cheng CHOU, Yu-Der CHIH
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Patent number: 11527285Abstract: A method of forming a filament in a resistive random-access memory (RRAM) device includes applying a cell voltage across a resistive layer of the RRAM device, detecting an increase in a current through the resistive layer generated in response to the applied cell voltage, and in response to detecting the increase in the current, using a first switching device to reduce the current through the resistive layer.Type: GrantFiled: March 12, 2021Date of Patent: December 13, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chung-Cheng Chou, Zheng-Jun Lin, Pei-Ling Tseng
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Publication number: 20220359008Abstract: A memory device includes a memory cell and a sense amplifier. The sense amplifier has a reference circuit configured to output a reference voltage and a sensing circuit connected to the memory cell. A comparator includes a first input and a second input, with the first input connected to the reference circuit to receive the reference voltage, and the second input connected to the memory cell.Type: ApplicationFiled: May 26, 2022Publication date: November 10, 2022Inventors: Zheng-Jun Lin, Chung-Cheng Chou, Pei-Ling Tseng
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Publication number: 20220359010Abstract: A method of operating a memory circuit includes generating a first voltage by a first amplifier circuit of a first driver circuit coupled to a first column of memory cells, and generating a first current in response to the first voltage. The first current includes a first set of leakage currents and a first write current. The method further includes generating, by a tracking circuit, a second set of leakage currents configured to track the first set of leakage currents of the first column of memory cells, and mirroring the first current in a first path with a second current in a second path by a first current mirror. The second current includes the second set of leakage currents and a second write current. The first write current corresponds to the second write current. The first set of leakage currents corresponds to the second set of leakage currents.Type: ApplicationFiled: July 22, 2022Publication date: November 10, 2022Inventors: Chin-I SU, Chung-Cheng CHOU, Yu-Der CHIH, Zheng-Jun LIN
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Patent number: 11495294Abstract: The disclosed invention presents a self-tracking reference circuit that compensates for IR drops and achieves the target resistance state at different temperatures after write operations. The disclosed self-tracking reference circuit includes a replica access path, a configurable resistor network, a replica selector mini-array and a step current generator that track PVT variations to provide a PVT tracking level for RRAM verify operation.Type: GrantFiled: November 30, 2020Date of Patent: November 8, 2022Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Zheng-Jun Lin, Chung-Cheng Chou, Yu-Der Chih, Pei-Ling Tseng