Patents by Inventor Zheng-Long CHEN
Zheng-Long CHEN has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240047575Abstract: A semiconductor device includes a substrate, a deep well, a doped region, a gate, and source and drain regions. The deep well is of a first conductivity type in the substrate. The doped region is in the deep well with an impurity of a second conductivity type. The field oxide is over the deep well and has a side interfaced with the doped region. The gate is over the field oxide. The source and drain regions are over the substrate and laterally separated at least in part by the doped region and the field oxide.Type: ApplicationFiled: October 18, 2023Publication date: February 8, 2024Applicants: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., TSMC CHINA COMPANY LIMITEDInventor: Zheng-Long CHEN
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Patent number: 11837659Abstract: An integrated circuit includes a drift region in a substrate, a drain in the substrate which includes a doped drain well, the doped drain well including a first zone, having a first concentration of a first dopant, and a second zone, having a second concentration of the first dopant, where the first concentration is smaller than the second concentration, and a gate electrode over the drift region and being separated from the doped drain well in a direction parallel to a top surface of the substrate by a distance greater than 0.Type: GrantFiled: February 2, 2021Date of Patent: December 5, 2023Assignees: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., TSMC CHINA COMPANY, LIMITEDInventor: Zheng Long Chen
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Patent number: 11824115Abstract: A semiconductor device includes a semiconductor substrate, a deep n-well, a field oxide, a gate structure, a p-type doped region, a source region, and a drain region. The deep n-well is in the semiconductor substrate. The field oxide is partially embedded in the deep n-well and having a tip corner in a position substantially level with a top surface of the semiconductor substrate. The gate structure is on the field oxide and laterally extends past the tip corner of the field oxide. The p-type doped region is in the deep n-well and is interfaced with the tip corner of the field oxide. The source region and a drain region are laterally separated at least in part by the p-type doped region and the field oxide.Type: GrantFiled: April 8, 2022Date of Patent: November 21, 2023Assignees: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., TSMC CHINA COMPANY LIMITEDInventor: Zheng-Long Chen
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Publication number: 20230352305Abstract: A semiconductor device includes substrate, a first gate structure, a second gate structure, and an epitaxy layer. The first gate structure and the second gate structure are over the substrate, in which the first gate structure and the second gate structure each comprises a shielding electrode, a gate electrode over the shielding electrode, and a first gate dielectric layer vertically separating the shielding electrode from the gate electrode. The epitaxy layer is over the substrate and cups an underside of the first gate structure and the second gate structure, in which the epitaxy layer comprises a doped region laterally between the first gate dielectric layer of the first gate structure and the first gate dielectric layer of the second gate structure, a dopant concentration of the doped region being non-uniform along a lateral direction.Type: ApplicationFiled: July 12, 2023Publication date: November 2, 2023Applicants: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., TSMC CHINA COMPANY LIMITEDInventor: Zheng-Long CHEN
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Patent number: 11742207Abstract: A semiconductor device includes substrate, a first gate structure, a second gate structure, and an epitaxy layer. The first gate structure and the second gate structure are over the substrate, in which the first gate structure and the second gate structure each comprises a shielding electrode, a gate electrode over the shielding electrode, and a first gate dielectric layer vertically separating the shielding electrode from the gate electrode. The epitaxy layer is over the substrate and cups an underside of the first gate structure and the second gate structure, in which the epitaxy layer comprises a doped region laterally between the first gate dielectric layer of the first gate structure and the first gate dielectric layer of the second gate structure, a dopant concentration of the doped region being non-uniform along a lateral direction.Type: GrantFiled: February 7, 2022Date of Patent: August 29, 2023Assignees: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., TSMC CHINA COMPANY LIMITEDInventor: Zheng-Long Chen
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Patent number: 11699752Abstract: A semiconductor device includes a first semiconductor region having a first conductivity type and a second semiconductor region having a second conductivity type, a source region and a body contact region in the second semiconductor region. The semiconductor device also includes a channel region, in the second semiconductor region, located laterally between the source region and the first semiconductor region, a gate dielectric layer overlying both the channel region and a portion of the first semiconductor region, and a gate electrode overlying the gate dielectric layer. The semiconductor device further includes a conformal conductive layer covering an upper surface of the body contact region and a side surface of the source region.Type: GrantFiled: February 2, 2021Date of Patent: July 11, 2023Assignees: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., TSMC CHINA COMPANY, LIMITEDInventor: Zheng Long Chen
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Publication number: 20230207694Abstract: A semiconductor device includes a substrate, a first well region in the substrate, a gate structure over the substrate, a second well region and a third well region in the substrate and under the gate structure, and a source region and a drain region on opposite sides of the gate structure. The drain region is in the second well region and the source region is in the third well region. The drain region has a first doped region and a second doped region, and the first doped region and the second doped region have different conductivity types.Type: ApplicationFiled: March 14, 2022Publication date: June 29, 2023Applicants: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., TSMC China Company LimitedInventors: Hang FAN, Feng HAN, Zheng Long CHEN, Jian-Hua LU
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Publication number: 20230056697Abstract: A method includes forming a dielectric layer on a substrate; forming a first spiral electrode, a second spiral electrode, and a spiral common electrode in the dielectric layer, the first spiral electrode extending in a first spiral path, the second spiral electrode extending in a second spiral path, and the spiral common electrode extending in a third spiral path laterally between the first and second spiral paths.Type: ApplicationFiled: October 28, 2022Publication date: February 23, 2023Applicants: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., TSMC CHINA COMPANY LIMITEDInventor: Zheng-Long CHEN
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Publication number: 20220384640Abstract: A method of manufacturing a semiconductor device includes forming a gate electrode overlying a gate dielectric layer covering both a channel region in a second semiconductor region and a portion of a first semiconductor region. First-type dopants are implemented into the second semiconductor region masked by a hard mask to form a source precursor region. The method also includes forming a spacer which overlies the source precursor region and has a first side laterally adjacent to the gate electrode, and recessing a surface region in the source precursor region masked by the spacer to form a source region. The method still includes implanting second-type dopants through the surface region masked at least by the spacer to form a body contact region, and forming a conformal conductive layer covering an upper surface of the body contact region and a side surface of the source.Type: ApplicationFiled: August 10, 2022Publication date: December 1, 2022Inventor: Zheng Long CHEN
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Publication number: 20220384646Abstract: A method of making an integrated circuit includes forming a drift region in a substrate, the drift region having a first dopant type; forming a drain well in the drift region, the drain well having the first dopant type. The drain well includes a first zone with a first concentration of the first dopant and a second zone having a second concentration of the first dopant different from the first concentration of the first dopant. The method further includes forming a source well in the substrate, the source well having a second dopant type opposite from the first dopant type, the source well being adjacent to the drift region in the substrate. The method includes forming a gate electrode over a top surface of the substrate over the drift region and the source well, and being laterally separated from the drain well. The method includes forming a drain low-density doped (LDD) region in the second zone of the drain well.Type: ApplicationFiled: August 10, 2022Publication date: December 1, 2022Inventor: Zheng Long CHEN
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Patent number: 11489039Abstract: A semiconductor device includes a capacitor. The capacitor includes a first electrode and a second electrode disposed in a first metal layer. The first electrode has a first end and a second end, and the first electrode has a spiral pattern extending outwards from the first end to the second end. The first electrode and the second electrode have a substantially equal spacing therebetween.Type: GrantFiled: June 22, 2020Date of Patent: November 1, 2022Assignees: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., TSMC CHINA COMPANY LIMITEDInventor: Zheng-Long Chen
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Publication number: 20220231166Abstract: A semiconductor device includes a semiconductor substrate, a deep n-well, a field oxide, a gate structure, a p-type doped region, a source region, and a drain region. The deep n-well is in the semiconductor substrate. The field oxide is partially embedded in the deep n-well and having a tip corner in a position substantially level with a top surface of the semiconductor substrate. The gate structure is on the field oxide and laterally extends past the tip corner of the field oxide. The p-type doped region is in the deep n-well and is interfaced with the tip corner of the field oxide. The source region and a drain region are laterally separated at least in part by the p-type doped region and the field oxide.Type: ApplicationFiled: April 8, 2022Publication date: July 21, 2022Applicants: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., TSMC CHINA COMPANY LIMITEDInventor: Zheng-Long CHEN
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Patent number: 11362198Abstract: A method of forming a semiconductor structure including: forming a drift well in a substrate, in which the drift well includes first dopants having a first conductivity type; forming an isolation structure over the drift well; forming a well region in the drift well and spaced apart from the isolation structure, such that a top portion of the drift well is between the well region and the isolation structure; doping the top portion with second dopants having a second conductivity type different from the first conductivity type, such that a doping concentration of the second dopants in the top portion is lower than a doping concentration of the first dopants in the top portion after doping the top portion; and forming a gate structure extending from the isolation structure to the well region and covering the top portion of the drift well.Type: GrantFiled: July 20, 2020Date of Patent: June 14, 2022Assignees: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., TSMC CHINA COMPANY LIMITEDInventor: Zheng-Long Chen
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Publication number: 20220165573Abstract: A semiconductor device includes substrate, a first gate structure, a second gate structure, and an epitaxy layer. The first gate structure and the second gate structure are over the substrate, in which the first gate structure and the second gate structure each comprises a shielding electrode, a gate electrode over the shielding electrode, and a first gate dielectric layer vertically separating the shielding electrode from the gate electrode. The epitaxy layer is over the substrate and cups an underside of the first gate structure and the second gate structure, in which the epitaxy layer comprises a doped region laterally between the first gate dielectric layer of the first gate structure and the first gate dielectric layer of the second gate structure, a dopant concentration of the doped region being non-uniform along a lateral direction.Type: ApplicationFiled: February 7, 2022Publication date: May 26, 2022Applicants: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., TSMC CHINA COMPANY LIMITEDInventor: Zheng-Long CHEN
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Publication number: 20220115534Abstract: A semiconductor device includes a first semiconductor region having a first conductivity type and a second semiconductor region having a second conductivity type, a source region and a body contact region in the second semiconductor region. The semiconductor device also includes a channel region, in the second semiconductor region, located laterally between the source region and the first semiconductor region, a gate dielectric layer overlying both the channel region and a portion of the first semiconductor region, and a gate electrode overlying the gate dielectric layer. The semiconductor device further includes a conformal conductive layer covering an upper surface of the body contact region and a side surface of the source region.Type: ApplicationFiled: February 2, 2021Publication date: April 14, 2022Inventor: Zheng Long CHEN
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Publication number: 20220115536Abstract: An integrated circuit includes a drift region in a substrate, a drain in the substrate which includes a doped drain well, the doped drain well including a first zone, having a first concentration of a first dopant, and a second zone, having a second concentration of the first dopant, where the first concentration is smaller than the second concentration, and a gate electrode over the drift region and being separated from the doped drain well in a direction parallel to a top surface of the substrate by a distance greater than 0.Type: ApplicationFiled: February 2, 2021Publication date: April 14, 2022Inventor: Zheng Long CHEN
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Patent number: 11302809Abstract: A method includes forming a first-type deep well with a first impurity of a first conductivity type in a semiconductor substrate; doping a second impurity of a second conductivity type into the first-type deep well to form a second-type doped region, in which a concentration of the first impurity in the first-type deep well is greater than a concentration of the second impurity in the second-type doped region and less than about ten times the concentration of the second impurity in the second-type doped region; forming a field oxide partially embedded in the semiconductor substrate, the field oxide laterally extending from a first side of the second-type doped region; forming a second-type well of the second conductivity type in the first-type deep well and on a second side of the second-type doped region opposite the first side of the second-type doped region.Type: GrantFiled: September 3, 2020Date of Patent: April 12, 2022Assignees: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., TSMC CHINA COMPANY LIMITEDInventor: Zheng-Long Chen
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Publication number: 20220059692Abstract: A method includes forming a first-type deep well with a first impurity of a first conductivity type in a semiconductor substrate; doping a second impurity of a second conductivity type into the first-type deep well to form a second-type doped region, in which a concentration of the first impurity in the first-type deep well is greater than a concentration of the second impurity in the second-type doped region and less than about ten times the concentration of the second impurity in the second-type doped region; forming a field oxide partially embedded in the semiconductor substrate, the field oxide laterally extending from a first side of the second-type doped region; forming a second-type well of the second conductivity type in the first-type deep well and on a second side of the second-type doped region opposite the first side of the second-type doped region.Type: ApplicationFiled: September 3, 2020Publication date: February 24, 2022Applicants: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., TSMC CHINA COMPANY LIMITEDInventor: Zheng-Long CHEN
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Patent number: 11244830Abstract: A method includes forming a hard mask over an epitaxy layer of a substrate; forming a patterned mask over the hard mask; etching the hard mask and the epitaxy layer to form a trench in the epitaxy layer, in which a remaining portion of the hard mask covers a topmost surface of the epitaxy layer, and the trench exposes a sidewall of the epitaxy layer; forming a P-well region by directing p-type ion beams into the trench along an oblique direction that is non-parallel to a normal line of the topmost surface of the epitaxy layer, in which the topmost surface of the epitaxy layer is protected from the p-type ion beams by the remaining portion of the hard mask during directing the p-type ion beams into the trench; and after directing the p-type ion beams into the trench, forming a gate structure in the trench.Type: GrantFiled: April 27, 2020Date of Patent: February 8, 2022Assignees: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., TSMC CHINA COMPANY LIMITEDInventor: Zheng-Long Chen
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Publication number: 20220005949Abstract: A method of forming a semiconductor structure including: forming a drift well in a substrate, in which the drift well includes first dopants having a first conductivity type; forming an isolation structure over the drift well; forming a well region in the drift well and spaced apart from the isolation structure, such that a top portion of the drift well is between the well region and the isolation structure; doping the top portion with second dopants having a second conductivity type different from the first conductivity type, such that a doping concentration of the second dopants in the top potion is lower than a doping concentration of the first dopants in the top portion after doping the top portion; and forming a gate structure extending from the isolation structure to the well region and covering the top portion of the drift well.Type: ApplicationFiled: July 20, 2020Publication date: January 6, 2022Applicants: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., TSMC CHINA COMPANY LIMITEDInventor: Zheng-Long CHEN