Abstract: A wireless communication method and apparatus are provided. One example method includes: receiving first PEI by a first terminal device, using, by the first terminal device, at least one of the first subgroup ID or the second subgroup ID.

Abstract: The present disclosure provides a method and a device for sidelink communication. One example method includes: performing, by a terminal device, channel listening on a shared spectrum; and in response to a result of the channel listening being idle channels, transmitting, by the terminal device, a first sidelink channel by using a consecutive-slots transmission; wherein the consecutive-slots transmission comprises a transmission over a plurality of consecutive time slots, a first transmission block carried by the first sidelink channel includes transmission data corresponding to the plurality of consecutive time slots.

Abstract: The present disclosure provides a method and a device for sidelink communication. One example method includes: a terminal device receives a first PSSCH; the terminal device performs channel access on the shared spectrum, where the first PSSCH is associated with a plurality of PSFCH transmission resources on the shared spectrum, and the plurality of PSFCH transmission resources are located on at least one of reserved resources or dynamic resources on the shared spectrum; the terminal device transmits a first PSFCH using one PSFCH transmission resource of the plurality of PSFCH transmission resources, where the first PSFCH carries feedback information associated with the first PSSCH.

Abstract: The present disclosure provides a method and a device for sidelink communication. One example method includes: a terminal device receives a first PSSCH; the terminal device performs channel access on the shared spectrum, where the first PSSCH is associated with a plurality of PSFCH transmission resources on the shared spectrum, and the plurality of PSFCH transmission resources are located on at least one of reserved resources or dynamic resources on the shared spectrum; the terminal device transmits a first PSFCH using one PSFCH transmission resource of the plurality of PSFCH transmission resources, where the first PSFCH carries feedback information associated with the first PSSCH.

Abstract: Provided are a communication method and a terminal device. The communication method includes: sending, by a first terminal device, a first sidelink channel to a second terminal device over a first sidelink, where the first sidelink channel includes first COT sharing information, and the first COT sharing information satisfies one or more of the following: the first COT sharing information is carried in a first PSSCH of the first sidelink channel; and the first COT sharing information includes second COT sharing information and third COT sharing information, with the second COT sharing information corresponding to a first communication mode, and the third COT sharing information corresponding to a second communication mode.

Abstract: A method and a device for wireless communication are provided. The method includes: a terminal device receiving first information sent by a network device, where the first information indicates a first timer, and the first timer has a first duration of performing small data transmission (SDT) using a first transmission resource, where the first duration is shorter than a second duration of a second timer, and the second duration is a duration related to a of SDT performed by the terminal device.

Abstract: A wireless communication method and apparatus are provided. One example method includes: receiving first PEI by a first terminal device, where the first PEI corresponds to at least one PO, and the first PEI is associated with first information, where the first information is used to indicate that a paging message in the at least one PO is a RAN-initiated paging message or a CN-initiated paging message.

Abstract: The present application provides a sidelink communication method and apparatus. The method includes: performing, by a terminal device, channel monitoring on shared spectrum; and if the result of the channel monitoring is that a channel is idle, starting, by the terminal device, transmission of a first sidelink channel at a first time domain position, where the first time domain position is one or more of the following: a time domain position indicated by first indication information; and a time domain position determined based on a first time unit, the first time unit being smaller than one slot.

Abstract: The present disclosure provides a method and a device for paging. A network device sends paging indication information including identification information to a plurality of terminal devices corresponding to a same beam. A first terminal device of the plurality of terminal devices determines whether it is paged by the network device according to the identification information. In response to the first terminal device being paged by the network device, the first terminal device sends a paging response message to the network device.

Abstract: The present disclosure relates to a method for manufacturing a CMOS structure. A first gate stack is formed on a semiconductor substrate in a first region. A second gate stack is formed on the semiconductor substrate in a second region. A dopant of a first type is implanted with the first gate stack and the second gate stack as a hard mask to form a lightly-doped drain region of the first type. A dopant of a second type is implanted by using a first mask and with the second gate stack as a hard mask to form a lightly-doped drain region of the second type. The first mask blocks the first region and exposes the second region. When the lightly-doped drain region of the second type is formed, the dopant of the second type over dopes a predetermined region of the lightly-doped drain region of the first type.

Abstract: The present disclosure relates to a method for manufacturing a CM OS structure. Shallow trench isolation is formed in a semiconductor substrate. A first region is defined for a first MOSFET and a second MOSFET of a first type and a second region is defined for a third MOSFET and a fourth MOSFET of a second type, by shallow trench isolation. First to fourth Gates sacks are formed on the semiconductor substrate, each of which includes a gate conductor and a gate dielectric and the gate dielectric is disposed between the gate conductor and the semiconductor substrate. The first and second gate stacks are formed in the first region, and the third and fourth gate stacks are formed in the second region. The gate dielectrics of the first and third gate stacks have a first thickness, and the gate dielectrics of the second and fourth gate stacks have a second thickness larger than the first thickness. Some masks are commonly used in various steps in this process so that the number of the masks is reduced.

Abstract: The present disclosure relates to a method for manufacturing a CMOS structure. A first gate stack is formed on a semiconductor substrate in a first region. A second gate stack is formed on the semiconductor substrate in a second region. A dopant of a first type is implanted with the first gate stack and the second gate stack as a hard mask to form a lightly-doped drain region of the first type. A dopant of a second type is implanted by using a first mask and with the second gate stack as a hard mask to form a lightly-doped drain region of the second type. The first mask blocks the first region and exposes the second region. When the lightly-doped drain region of the second type is formed, the dopant of the second type over dopes a predetermined region of the lightly-doped drain region of the first type. In such a process, over doping is used for reducing the number of masks. A doping concentration of a well region may be modified to adjust work function.

Abstract: The present disclosure relates to a lateral double-diffused metal oxide semiconductor transistor and a method for manufacturing the same. In the method, a high-voltage gate dielectric is formed at a surface of a semiconductor layer. A thin gate dielectric is formed above the substrate and has at least a portion adjacent to the high-voltage gate dielectric. A gate conductor is formed above the thin gate dielectric and the high-voltage gate dielectric. A first mask is used for patterning the gate conductor to define a first sidewall of the gate conductor above the thin gate dielectric. A second mask is used for patterning the gate conductor to define a second sidewall of the gate conductor at least partially above the high-voltage gate dielectric. Source and drain regions are formed to have a first doping type. The method further comprises doping through the first mask to form a body region of a second doping type. The second doping type is opposite to the first doping type.

Abstract: The present disclosure relates to a lateral double-diffused metal oxide semiconductor transistor and a method for manufacturing the same. In the method, a high-voltage gate dielectric is formed at a surface of a semiconductor layer. A thin gate dielectric is formed above the substrate and has at least a portion adjacent to the high-voltage gate dielectric. A gate conductor is formed above the thin gate dielectric and the high-voltage gate dielectric. A first mask is used for patterning the gate conductor to define a first sidewall of the gate conductor above the thin gate dielectric. A second mask is used for patterning the gate conductor to define a second sidewall of the gate conductor at least partially above the high-voltage gate dielectric. Source and drain regions are formed to have a first doping type. The method further comprises doping through the first mask to form a body region of a second doping type. The second doping type is opposite to the first doping type.

Abstract: The present disclosure relates to a method for manufacturing a CMOS structure. A first gate stack is formed on a semiconductor substrate in a first region. A second gate stack is formed on the semiconductor substrate in a second region. A dopant of a first type is implanted with the first gate stack and the second gate stack as a hard mask to form a lightly-doped drain region of the first type. A dopant of a second type is implanted by using a first mask and with the second gate stack as a hard mask to form a lightly-doped drain region of the second type. The first mask blocks the first region and exposes the second region. When the lightly-doped drain region of the second type is formed, the dopant of the second type over dopes a predetermined region of the lightly-doped drain region of the first type. In such a process, over doping is used for reducing the number of masks. A doping concentration of a well region may be modified to adjust work function.

Abstract: The present disclosure relates to a method for manufacturing a CM OS structure. Shallow trench isolation is formed in a semiconductor substrate. A first region is defined for a first MOSFET and a second MOSFET of a first type and a second region is defined for a third MOSFET and a fourth MOSFET of a second type, by shallow trench isolation. First to fourth Gates sacks are formed on the semiconductor substrate, each of which includes a gate conductor and a gate dielectric and the gate dielectric is disposed between the gate conductor and the semiconductor substrate. The first and second gate stacks are formed in the first region, and the third and fourth gate stacks are formed in the second region. The gate dielectrics of the first and third gate stacks have a first thickness, and the gate dielectrics of the second and fourth gate stacks have a second thickness larger than the first thickness. Some masks are commonly used in various steps in this process so that the number of the masks is reduced.