Abstract: Novel compounds of the structural formula (I), and the pharmaceutically acceptable salts thereof, are inhibitors of NLRP3 and may be useful in the treatment, prevention, management, amelioration, control and suppression of diseases mediated by NLPR3. The compounds of the present invention may be useful in the treatment, prevention or management of diseases, disorders and conditions mediated by NLRP3 such as, but not limited to, gout, pseudogout, CAPS, NASH fibrosis, heart failure, idiopathic pericarditis, atopic dermatitis, inflammatory bowel disease, Alzheimer's Disease, Parkinson's Disease and traumatic brain injury.

Abstract: Methods, systems, and apparatus, including computer programs encoded on computer storage media, for controlling, by an on-chip memory controller, a plurality of hardware components that are configured to perform computations to access a shared memory. One of the on-chip memory controller includes at least one backside arbitration controller communicatively coupled with a memory bank group and a first hardware component, wherein the at least one backside arbitration controller is configured to perform bus arbitrations to determine whether the first hardware component can access the memory bank group using a first memory access protocol; and a frontside arbitration controller communicatively coupled with the memory bank group and a second hardware component, wherein the frontside arbitration controller is configured to perform bus arbitrations to determine whether the second hardware component can access the memory bank group using a second memory access protocol different from the first memory access protocol.

Abstract: An extensible multi-precision data pipeline system, comprising, a local buffer that stores an input local data set in a local storage format, an input tensor shaper coupled to the local buffer that reads the input local data set and converts the input local data set into an input tensor data set having a tensor format of vector width N by tensor length L, a cascaded pipeline coupled to the input tensor shaper that routes the input tensor data set through at least one function stage resulting in an output tensor data set, an output tensor shaper coupled to the cascaded pipeline that converts the output tensor data set into an output local data set having the local storage format and wherein the output tensor shaper writes the output local data set to the local buffer.

Abstract: The present invention discloses a graph partitioning system for running neural networks on resource constrained hardware systems. The graph partitioning system used for partitioning a neural network graph into a series of sub-graphs and further allow the multiple sub-graphs to be executed in available hardware subsystems. The system based on cost function as estimated computation time and memory bandwidth of partitioned sub-graphs. The graph partitioning system is a cycle estimation model of hardware that can run fast and parameterize memory latency. The graph partitioning system supports heterogeneous partition for different type accelerators such as CPU, GPU, ASIC. The present invention also discloses a method for partitioning neural network graph in to series of sub-graphs.

Abstract: Methods, systems, and apparatus, including computer programs encoded on computer storage media, for controlling, by an on-chip memory controller, a plurality of hardware components that are configured to perform computations to access a shared memory. One of the on-chip memory controller includes at least one backside arbitration controller communicatively coupled with a memory bank group and a first hardware component, wherein the at least one backside arbitration controller is configured to perform bus arbitrations to determine whether the first hardware component can access the memory bank group using a first memory access protocol; and a frontside arbitration controller communicatively coupled with the memory bank group and a second hardware component, wherein the frontside arbitration controller is configured to perform bus arbitrations to determine whether the second hardware component can access the memory bank group using a second memory access protocol different from the first memory access protocol.

Abstract: The present invention relates to a method and a system for performing depthwise separable convolution on an input data in a convolutional neural network. The invention utilizes a heterogeneous architecture with a number of MAC arrays including 1D MAC arrays and 2D MAC arrays with a Winograd conversion logic to perform depthwise separable convolution. The depthwise separable convolution uses less weight parameters and thus less multiplications while it obtains the same computation results as the traditional convolution.

Abstract: The present invention relates to convolution neural networks (CNN) and methods for improving computational efficiency of multiply accumulate (MAC) array structure Specifically, the invention relates to cutting of activation data into a number of tiles for increasing overall computation efficiency. The invention discloses techniques to cut an activation data into a plurality of tiles by using a 3-D convolution computation core and support bigger tensor sizes. Lastly, the invention provides adaptive scheduling of MAC array to achieve high utilization in multi-precision neural network acceleration.

Abstract: A system on a chip, including a first domain having a first processor, a first local memory coupled to the first processor, wherein the first local memory having a first memory format and a first sub-network coupled to the first processor, a second domain having a second processor, a second local memory coupled to the second processor and a second sub-network coupled to the second processor, wherein the second local memory having a second memory format which differs from the first memory format, a multi-tier network coupled to the first sub-network and the second sub-network, a global memory coupled to the multi-tier network and a multi-port DDR controller coupled to the global memory to receive, transmit and share the first local memory having the first memory format and the second local memory having the second memory format based on a predetermined criteria.

Abstract: A method of constructing sub-graphs, includes receiving a directed acyclic graph (DAG), partitioning the directed acyclic graph into an at least one section, determining at least one hardware attribute, determining at least one DAG hardware limitation of the at least one section and determining a largest continuous node list of the at least one section in which the at least one hardware attribute meets the at least one DAG hardware limitation.

Abstract: A method of quantization evaluation, including, receiving a floating point data set, determining a floating point neural network model output utilizing the floating point data set, quantizing the floating point data set utilizing a quantization model yielding a quantized data set, determining a quantized neural network model output utilizing the quantized data set, determining whether an accuracy error between the floating point neural network model output and the quantized neural network model output exceeds an predetermined error tolerance, determining a floating point neural network tensor output utilizing the floating point data set if the predetermined error tolerance is exceeded, determining a quantized neural network tensor output utilizing the quantized data set if the predetermined error tolerance is exceeded, determining a per-tensor error based on the floating point neural network tensor output and the quantized neural network tensor output and updating the quantization model based on the per-tenso

Abstract: The invention discloses a method and a system for achieving a unified flow control system for multiple camera devices. The system provides inline and offline streams to share resources by converting the streams into one another. The resource sharing is performed by using different time interval to process inline and offline streams. The system also includes a STALL & REDO operation to keep whole image un-broken and shut down the write stream from ISP right away.

Abstract: A method of wheel encoder to camera calibration, including receiving a LiDAR (Light Detection and Ranging) signal, receiving a camera signal, receiving a wheel encoder signal, calibrating the camera signal to the LiDAR signal, calibrating the wheel encoder signal to the LiDAR signal and calibrating the camera signal to the wheel encoder signal based on the calibration of the camera signal to the LiDAR signal and the wheel encoder signal to the LiDAR signal.

Abstract: A method of wheel encoder to camera calibration, including receiving a LiDAR (Light Detection and Ranging) signal, receiving a camera signal, receiving a wheel encoder signal, calibrating the camera signal to the LiDAR signal, calibrating the wheel encoder signal to the LiDAR signal and calibrating the camera signal to the wheel encoder signal based on the calibration of the camera signal to the LiDAR signal and the wheel encoder signal to the LiDAR signal.

Abstract: An example method of image signal processing, comprising at least one of, receiving a set of high priority signals, receiving a set of low priority signals, reconfiguring a first portion of a pipeline to route the high priority signals through an in-line mode process and reconfiguring a second portion of the pipeline to route the low priority signals through an offline mode process.

Abstract: An example fused convolutional layer, comprising, a comparator capable of reception of a first zero point and a multiply-accumulation result, a first multiplexer coupled to the comparator, wherein the first multiplexer receives a plurality of power-of-two exponent values, a shift normalizer, coupled to the first multiplexer, wherein the shift normalizer is capable of receiving the multiply-accumulation result and the plurality of power-of-two exponent values, wherein the shift normalizer limits a quantization of the multiply-accumulation result to a power-of-two scale and a second multiplexer coupled to an output of the shift normalizer, the first multiplexer and receives a second zero point and outputs an activation.

Abstract: An extensible multi-precision data pipeline system, comprising, a local buffer that stores an input local data set in a local storage format, an input tensor shaper coupled to the local buffer that reads the input local data set and converts the input local data set into an input tensor data set having a tensor format of vector width N by tensor length L, a cascaded pipeline coupled to the input tensor shaper that routes the input tensor data set through at least one function stage resulting in an output tensor data set, an output tensor shaper coupled to the cascaded pipeline that converts the output tensor data set into an output local data set having the local storage format and wherein the output tensor shaper writes the output local data set to the local buffer.

Abstract: An example method of image signal processing, comprising at least one of, receiving a set of high priority signals, receiving a set of low priority signals, reconfiguring a first portion of a pipeline to route the high priority signals through an in-line mode process and reconfiguring a second portion of the pipeline to route the low priority signals through an offline mode process.

Abstract: A system on a chip, including a first domain having a first processor, a first local memory coupled to the first processor, wherein the first local memory having a first memory format and a first sub-network coupled to the first processor, a second domain having a second processor, a second local memory coupled to the second processor and a second sub-network coupled to the second processor, wherein the second local memory having a second memory format which differs from the first memory format, a multi-tier network coupled to the first sub-network and the second sub-network, a global memory coupled to the multi-tier network and a multi-port DDR controller coupled to the global memory to receive, transmit and share the first local memory having the first memory format and the second local memory having the second memory format based on a predetermined criteria.

Abstract: A system on a chip, including a multi-port memory controller having a multi-level memory hierarchy, a multi-tier bus coupled to the multi-port memory controller to segregate memory access traffic based on the multi-level memory hierarchy, an interconnected plurality of networks on chip coupled to the multi-tier bus, a plurality of networked domains coupled to the plurality of networks on chip and at least one non-networked domain coupled directly to the multi-port memory controller.

Abstract: A method and system for secure and scalable key management for cryptographic processing of data is described herein. A method of secure key handling and cryptographic processing of data, comprising receiving a request from an entity to cryptographically process a block of data, the request including a key handle, wherein the key handle includes an authentication tag and an index; authenticating the requesting entity using the authentication tag; and referencing a plaintext key from a plurality of plaintext keys using the index if the requesting entity is authenticated successfully.