Abstract: A die package comprises a substrate comprising a first face and an opposing second face, a first semiconductor die coupled to the first face of the substrate, a second semiconductor die coupled to the first face of the substrate; and a heat spreader, wherein the first semiconductor die is thermally connected to the heat spreader by a first thermal interface material and the second semiconductor die is thermally connected to the heat spreader by a second thermal interface material, wherein the first thermal interface material comprises a first composition and the second thermal interface material comprises a second composition, wherein the first composition has a lower elastic modulus than the second composition under a first specified condition or conditions.

Abstract: Disclosed are a group of single nucleotide polymorphism (SNP) loci and a method for identifying biogeographic origins of East Asian populations, and belong to the technical field of gene identification. The application takes single nucleotide polymorphism molecular genetic markers as objects, systematically selects loci with high genetic differentiation in the East Asian populations of Beijing Han population, Southern Han population, Dai population, Japanese and Kinh Population from Vietnam, and constructs an efficient, simple and fast artificial intelligence model through the XGBoost machine learning algorithm for analyzing biogeographic origins of five East Asian populations.

Abstract: A control system for an air outlet of an air conditioner in a vehicle includes a motor, a first clutch configured to control a horizontal vane of the air outlet, a second clutch configured to control a longitudinal vane of the air outlet, a third clutch configured to control an opening degree of a ventilation door of the air outlet, and an engaging element of the motor being connected to the motor, for engaging the clutches. The motor adjusts the horizontal vane of the air outlet when the engaging element is engaged with the first clutch, the motor adjusts the longitudinal vane of the air outlet when the engaging element is engaged with the second clutch, and the motor adjusts the opening degree of the ventilation door of the air outlet when the engaging element of the motor is engaged with the third clutch.

Abstract: The present disclosure provides a global shutter CMOS pixel circuit and its image capturing method. The global shutter CMOS pixel circuit comprising a power supply unit, a pixel signal generating unit, a signal sampling and holding unit and a signal outputting unit. An output of the pixel signal generating unit is connected to an input of the signal sampling and holding unit. An output of the signal sampling and holding unit is connected to an input of the signal outputting unit. The output signal of the pixel and the photo-generated current are set to a logarithmic relationship, which effectively increases the signal dynamic range. Therefore, image signal transmission with high speed and high dynamic range can be achieved simultaneously. Furthermore, the pixels in the present disclosure can eliminate the process variations, which increases the consistency of the pixels.

Abstract: A control system for an air outlet of air conditioner in a vehicle includes a motor, a first clutch configured to control a horizontal vane of the air outlet, a second clutch configured to control a longitudinal vane of the air outlet, a third clutch configured to control an opening degree of a ventilation door of the air outlet, and an engaging element of the motor being connected to the motor, for engaging the clutches. The motor adjusts the horizontal vane of the air outlet when the engaging element is engaged with the first clutch, the motor adjusts the longitudinal vane of the air outlet when the engaging element is engaged with the second clutch, and the motor adjusts the opening degree of the ventilation door of the air outlet when the engaging element of the motor is engaged with the third clutch.

Abstract: The present disclosure provides a global shutter CMOS pixel circuit and its image capturing method. The global shutter CMOS pixel circuit comprising a power supply unit, a pixel signal generating unit, a signal sampling and holding unit and a signal outputting unit. An output of the pixel signal generating unit is connected to an input of the signal sampling and holding unit. An output of the signal sampling and holding unit is connected to an input of the signal outputting unit. The output signal of the pixel and the photo-generated current are set to a logarithmic relationship, which effectively increases the signal dynamic range. Therefore, image signal transmission with high speed and high dynamic range can be achieved simultaneously. Furthermore, the pixels in the present disclosure can eliminate the process variations, which increases the consistency of the pixels.

Abstract: A metal oxide nanorod array structure according to embodiments disclosed herein includes a monolithic substrate having a surface and multiple channels, an interface layer bonded to the surface of the substrate, and a metal oxide nanorod array coupled to the substrate surface via the interface layer. The metal oxide can include ceria, zinc oxide, tin oxide, alumina, zirconia, cobalt oxide, and gallium oxide. The substrate can include a glass substrate, a plastic substrate, a silicon substrate, a ceramic monolith, and a stainless steel monolith. The ceramic can include cordierite, alumina, tin oxide, and titania. The nanorod array structure can include a perovskite shell, such as a lanthanum-based transition metal oxide, or a metal oxide shell, such as ceria, zinc oxide, tin oxide, alumina, zirconia, cobalt oxide, and gallium oxide, or a coating of metal particles, such as platinum, gold, palladium, rhodium, and ruthenium, over each metal oxide nanorod.

Abstract: A cable tray junction includes floor panel and a post secured to the floor panel. The post includes a splice plate connector defining a female coupling component. A splice plate interconnects the post and a cable tray. The splice plate includes a post connector, which defines a male coupling component received in the female coupling component to connect the splice plate to the post without the use of a separate fastener. The splice plate connector may have a curved groove and the post connector may have a tongue received in the curved groove. A wall panel connector of the post defines a wall panel groove in which a wall panel is received to connect the wall panel to the post.

Abstract: A method is provided for designing an IC chip. The method includes receiving data from a pre-layout design process for the IC chip, routing a plurality of interconnecting wires to connect various devices of the IC chip, and extracting various circuit parameters. The method also includes simulating the IC chip using the extracted various circuit parameters to detect logic or timing error in the IC chip. The extracting the various circuit parameters includes establishing a statistical interconnect technology profile (ITP) file containing at least interconnect parasitic parameters based on correlations of interconnect layer geometric parameter variations.

Abstract: A manufacturing method is provided for fabricating a vertical channel gate-all-around MOSFET by epitaxy processes. The method includes growing a first epitaxial layer on a top semiconducting layer of a substrate; etching the first epitaxial layer and the top layer to form a first source/drain pattern in the top layer; etching the first epitaxial layer to form a vertical channel structure; then forming a gate dielectric layer on the vertical channel structure surface; forming a sandwich structure composed of a bottom spacer layer, a gate electrode layer and a top spacer layer; etching the top spacer layer and the gate electrode layer to form a gate pattern followed by forming a top spacer structure thereon; growing a second epitaxial layer and etching to form a second source/drain pattern.

Abstract: A manufacturing method is provided for fabricating a vertical channel gate-all-around MOSFET by epitaxy processes. The method includes growing a first epitaxial layer on a top semiconducting layer of a substrate; etching the first epitaxial layer and the top layer to form a first source/drain pattern in the top layer; etching the first epitaxial layer to form a vertical channel structure; then forming a gate dielectric layer on the vertical channel structure surface; forming a sandwich structure composed of a bottom spacer layer, a gate electrode layer and a top spacer layer; etching the top spacer layer and the gate electrode layer to form a gate pattern followed by forming a top spacer structure thereon; growing a second epitaxial layer and etching to form a second source/drain pattern.

Abstract: A cable tray junction includes floor panel and a post secured to the floor panel. The post includes a splice plate connector defining a female coupling component. A splice plate interconnects the post and a cable tray. The splice plate includes a post connector, which defines a male coupling component received in the female coupling component to connect the splice plate to the post without the use of a separate fastener. The splice plate connector may have a curved groove and the post connector may have a tongue received in the curved groove. A wall panel connector of the post defines a wall panel groove in which a wall panel is received to connect the wall panel to the post.

Abstract: A method is provided for designing an IC chip. The method includes receiving data from a pre-layout design process for the IC chip, routing a plurality of interconnecting wires to connect various devices of the IC chip, and extracting various circuit parameters. The method also includes simulating the IC chip using the extracted various circuit parameters to detect logic or timing error in the IC chip. The extracting the various circuit parameters includes establishing a statistical interconnect technology profile (ITP) file containing at least interconnect parasitic parameters based on correlations of interconnect layer geometric parameter variations.

Abstract: A metal oxide nanorod array structure according to embodiments disclosed herein includes a monolithic substrate having a surface and multiple channels, an interface layer bonded to the surface of the substrate, and a metal oxide nanorod array coupled to the substrate surface via the interface layer. The metal oxide can include ceria, zinc oxide, tin oxide, alumina, zirconia, cobalt oxide, and gallium oxide. The substrate can include a glass substrate, a plastic substrate, a silicon substrate, a ceramic monolith, and a stainless steel monolith. The ceramic can include cordierite, alumina, tin oxide, and titania. The nanorod array structure can include a perovskite shell, such as a lanthanum-based transition metal oxide, or a metal oxide shell, such as ceria, zinc oxide, tin oxide, alumina, zirconia, cobalt oxide, and gallium oxide, or a coating of metal particles, such as platinum, gold, palladium, rhodium, and ruthenium, over each metal oxide nanorod.