Patents by Inventor Zheng Ren
Zheng Ren has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11979916Abstract: Disclosed are a method and apparatus for determining an RA-RNTI. In the present application, a base station receives a random access preamble sent by a terminal; the base station determines an RA-RNTI according to a time-frequency resource occupied by the random access preamble, and the time-frequency resource is a time-frequency resource of an orthogonal frequency division multiplexing (OFDM) symbol level; and the base station sends a random access response message, and the random access response message includes downlink control information allocated, by the base station, for the terminal, and the downlink control information is scrambled using the RA-RNTI. By means of the present application, an RA-RNTI can be determined during a random access process of an NR system.Type: GrantFiled: June 14, 2023Date of Patent: May 7, 2024Assignee: DATANG MOBILE COMMUNICATIONS EQUIPMENT CO., LTD.Inventors: Bin Ren, Zheng Zhao, Ren Da, Tie Li, Fang-Chen Cheng
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Publication number: 20240127186Abstract: An interaction method and apparatus and an electronic device. The method comprises: displaying a first application interface, wherein the first application interface comprises an interface of a first application; and creating a second application account in the first application interface, wherein the second application account is used for logging in a second application. Therefore, a new interaction mode is provided.Type: ApplicationFiled: December 21, 2023Publication date: April 18, 2024Inventors: Xiaoping ZHANG, Yunsheng HAO, Jialu WANG, Yi WEI, Pengzhan XU, Guichao REN, Boyu ZHOU, Zitian GUO, Yuxiang LI, Jieli LIANG, Xiaofei GAO, Daozhi LIN, Hong ZOU, Wentao LIU, Zheng CHEN, Shanshan LING
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Patent number: 11954210Abstract: A hierarchical health index evaluation method for an intelligent substation includes: obtaining a basic health index of a device based on static information and dynamic information of the device; obtaining a device correlation based on a communication connection relationship between the device and another device, and correcting the basic health index of the device based on the device correlation to obtain a health index of the device; obtaining a layer-based health index of a layer based on a device health index and a device importance weight of the layer; obtaining a whole-station health index of an intelligent substation based on a layer-based health index of each layer and a sum of device importance weights of each layer; and regulating the intelligent substation based on a health index of each device in the intelligent substation, the layer-based health index of each layer, and the whole-station health index.Type: GrantFiled: December 29, 2021Date of Patent: April 9, 2024Assignees: State Grid Shandong Electric Power Research Institute, State Grid Corporation of ChinaInventors: Wenting Wang, Zheng Xu, Xin Liu, Yujie Geng, Qigui Nie, Lin Lin, Jing Liu, Guodong Lv, Yang Zhao, Tiancheng Ren, Xiaohong Zhao
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Publication number: 20240113809Abstract: The present application provides an instruction encoding-based data processing method and apparatus, and a device. N-path error correction encoding is performed on an instruction in information to be processed to obtain N encoded instructions, the encoded instructions and encoded meta channel programs obtained by the error correction encoding are used to perform redundant processing on data to be processed to obtain N pieces of response data, and then error correction decoding is performed on the N pieces of response data to obtain processing result information of the information to be processed. Because the N encoded instructions are heterogeneous and the encoded meta channel programs used in the N-path processing are heterogeneous, the randomness of the processing process can be improved, generalized disturbance in the data processing process can be corrected in combination with the error correction encoding and decoding methods, and thus the security of data processing is improved.Type: ApplicationFiled: June 7, 2021Publication date: April 4, 2024Inventors: Lei HE, Jiangxing WU, Quan REN, Zhen ZHANG, Weitao HAN, Fengyu ZHANG, Zheng YUAN, Yiwei GUO, Zhifeng FENG
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Publication number: 20240086690Abstract: The present disclosure relates to a spike event decision-making device, method, chip, and electronic device to eliminate inherent delays of an output spike event of the neuromorphic chip when reading decisions. The spike event decision-making device includes a first counting module configured to count a number of input spike events of the spiking neural network, a second counting module configured to count some or all of the output spike events of the spiking neural network; and a decision-making module configured to generate a decision-making result according to numbers of spike events fired by neurons in an output layer of the spiking neural network when the number counted by the first counting module reaches a first predetermined value, or when the total count counted by the second counting module reaches a second predetermined value.Type: ApplicationFiled: January 14, 2022Publication date: March 14, 2024Applicants: Chengdu SynSense Technology Co., Ltd., ShenZhen SynSense Technology Co., Ltd.Inventors: Peng ZHOU, Yannan XING, Ning QIAO, Yudi REN, Zheng KE, Yalun HU, Bo LI, Yuhang LIU, Xiwen GONG, Sadique UI Ameen SHEIK, Dylan RICHARD MUIR, Tugba DEMIRCI
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Publication number: 20240088631Abstract: Provided are an overhead line detection method and system based on a cable inspection robot. The cable inspection robot is suspended on the overhead line. An imaging unit and a laser emission unit are disposed at the front end of the cable inspection robot. The imaging unit is at a first angle to the overhead line. The laser emission unit is at a second angle to the overhead line.Type: ApplicationFiled: November 28, 2022Publication date: March 14, 2024Inventors: Jiazhen DUAN, Zheng LU, Hongtao LIU, Ruxin SHI, Wei ZHANG, Yuqin SHU, Zhiwei KAN, Yannan CHEN, Xiaoqiang CHEN, Xianming REN
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Patent number: 11923891Abstract: Disclosed are a non-orthogonal multiple access (NOMA) multi-layer transmission method and an apparatus therefor. The method includes: a terminal determines a spread spectrum sequence group for NOMA multi-layer transmission, with the terminal being configured for NOMA multi-layer transmission, and the spread spectrum sequence group includes N spread spectrum sequences, the N spread spectrum sequences correspond to N data layers, the N spread spectrum sequences are mutually orthogonal, N is the number of data layers of NOMA multi-layer transmission, and N is an integer greater than 1; and the terminal sends data, the data comprising the N data layers using the spread spectrum sequence group for spectrum spreading.Type: GrantFiled: January 13, 2020Date of Patent: March 5, 2024Assignee: DATANG MOBILE COMMUNICATIONS EQUIPMENT CO.,LTD.Inventors: Xiangli Lin, Zheng Zhao, Bin Ren, Yanping Xing
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Publication number: 20240006378Abstract: A die package comprises a substrate comprising a first face and an opposing second face, a first semiconductor die coupled to the first face of the substrate, a second semiconductor die coupled to the first face of the substrate; and a heat spreader, wherein the first semiconductor die is thermally connected to the heat spreader by a first thermal interface material and the second semiconductor die is thermally connected to the heat spreader by a second thermal interface material, wherein the first thermal interface material comprises a first composition and the second thermal interface material comprises a second composition, wherein the first composition has a lower elastic modulus than the second composition under a first specified condition or conditions.Type: ApplicationFiled: June 30, 2022Publication date: January 4, 2024Inventors: Sergio Antonio Chan Arguedas, Zheng Ren, Arifur Chowdhury
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Publication number: 20230352116Abstract: Disclosed are a group of single nucleotide polymorphism (SNP) loci and a method for identifying biogeographic origins of East Asian populations, and belong to the technical field of gene identification. The application takes single nucleotide polymorphism molecular genetic markers as objects, systematically selects loci with high genetic differentiation in the East Asian populations of Beijing Han population, Southern Han population, Dai population, Japanese and Kinh Population from Vietnam, and constructs an efficient, simple and fast artificial intelligence model through the XGBoost machine learning algorithm for analyzing biogeographic origins of five East Asian populations.Type: ApplicationFiled: April 25, 2023Publication date: November 2, 2023Inventors: Xiaoye JIN, Jiang HUANG, Guiyin ZHOU, Zheng REN, Hongling ZHANG, Qiyan WANG, Yubo LIU, Jingyan JI, Bing XIA
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Patent number: 11448417Abstract: A control system for an air outlet of an air conditioner in a vehicle includes a motor, a first clutch configured to control a horizontal vane of the air outlet, a second clutch configured to control a longitudinal vane of the air outlet, a third clutch configured to control an opening degree of a ventilation door of the air outlet, and an engaging element of the motor being connected to the motor, for engaging the clutches. The motor adjusts the horizontal vane of the air outlet when the engaging element is engaged with the first clutch, the motor adjusts the longitudinal vane of the air outlet when the engaging element is engaged with the second clutch, and the motor adjusts the opening degree of the ventilation door of the air outlet when the engaging element of the motor is engaged with the third clutch.Type: GrantFiled: June 4, 2020Date of Patent: September 20, 2022Assignee: FAURECIA (CHINA) HOLDING CO., LTD.Inventors: Chenghao Wan, Zheng Ren, Ning Xu
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Patent number: 10939059Abstract: The present disclosure provides a global shutter CMOS pixel circuit and its image capturing method. The global shutter CMOS pixel circuit comprising a power supply unit, a pixel signal generating unit, a signal sampling and holding unit and a signal outputting unit. An output of the pixel signal generating unit is connected to an input of the signal sampling and holding unit. An output of the signal sampling and holding unit is connected to an input of the signal outputting unit. The output signal of the pixel and the photo-generated current are set to a logarithmic relationship, which effectively increases the signal dynamic range. Therefore, image signal transmission with high speed and high dynamic range can be achieved simultaneously. Furthermore, the pixels in the present disclosure can eliminate the process variations, which increases the consistency of the pixels.Type: GrantFiled: November 22, 2017Date of Patent: March 2, 2021Assignees: SHANGHAI IC R&D CENTER CO., LTD, CHENGDU IMAGE DESIGN TECHNOLOGY CO. LTD.Inventors: Jiebin Duan, Zheng Ren, Yu Jiang, Jianxin Wen, Changming Pi
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Publication number: 20210018213Abstract: A control system for an air outlet of air conditioner in a vehicle includes a motor, a first clutch configured to control a horizontal vane of the air outlet, a second clutch configured to control a longitudinal vane of the air outlet, a third clutch configured to control an opening degree of a ventilation door of the air outlet, and an engaging element of the motor being connected to the motor, for engaging the clutches. The motor adjusts the horizontal vane of the air outlet when the engaging element is engaged with the first clutch, the motor adjusts the longitudinal vane of the air outlet when the engaging element is engaged with the second clutch, and the motor adjusts the opening degree of the ventilation door of the air outlet when the engaging element of the motor is engaged with the third clutch.Type: ApplicationFiled: June 4, 2020Publication date: January 21, 2021Inventors: Chenghao WAN, Zheng REN, Ning XU
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Publication number: 20200007801Abstract: The present disclosure provides a global shutter CMOS pixel circuit and its image capturing method. The global shutter CMOS pixel circuit comprising a power supply unit, a pixel signal generating unit, a signal sampling and holding unit and a signal outputting unit. An output of the pixel signal generating unit is connected to an input of the signal sampling and holding unit. An output of the signal sampling and holding unit is connected to an input of the signal outputting unit. The output signal of the pixel and the photo-generated current are set to a logarithmic relationship, which effectively increases the signal dynamic range. Therefore, image signal transmission with high speed and high dynamic range can be achieved simultaneously. Furthermore, the pixels in the present disclosure can eliminate the process variations, which increases the consistency of the pixels.Type: ApplicationFiled: November 22, 2017Publication date: January 2, 2020Inventors: Jiebin DUAN, Zheng REN, Yu JIANG, Jianxin WEN, Changming PI
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Patent number: 9855549Abstract: A metal oxide nanorod array structure according to embodiments disclosed herein includes a monolithic substrate having a surface and multiple channels, an interface layer bonded to the surface of the substrate, and a metal oxide nanorod array coupled to the substrate surface via the interface layer. The metal oxide can include ceria, zinc oxide, tin oxide, alumina, zirconia, cobalt oxide, and gallium oxide. The substrate can include a glass substrate, a plastic substrate, a silicon substrate, a ceramic monolith, and a stainless steel monolith. The ceramic can include cordierite, alumina, tin oxide, and titania. The nanorod array structure can include a perovskite shell, such as a lanthanum-based transition metal oxide, or a metal oxide shell, such as ceria, zinc oxide, tin oxide, alumina, zirconia, cobalt oxide, and gallium oxide, or a coating of metal particles, such as platinum, gold, palladium, rhodium, and ruthenium, over each metal oxide nanorod.Type: GrantFiled: September 28, 2012Date of Patent: January 2, 2018Assignee: UNIVERSITY OF CONNECTICUTInventors: Pu-Xian Gao, Yanbing Guo, Zheng Ren
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Patent number: 9625669Abstract: A cable tray junction includes floor panel and a post secured to the floor panel. The post includes a splice plate connector defining a female coupling component. A splice plate interconnects the post and a cable tray. The splice plate includes a post connector, which defines a male coupling component received in the female coupling component to connect the splice plate to the post without the use of a separate fastener. The splice plate connector may have a curved groove and the post connector may have a tongue received in the curved groove. A wall panel connector of the post defines a wall panel groove in which a wall panel is received to connect the wall panel to the post.Type: GrantFiled: September 12, 2014Date of Patent: April 18, 2017Assignee: Cooper Technologies CompanyInventors: Brandon Michael Tally, Stephen Nathaniel Thompson, Zheng Ren
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Patent number: 9471739Abstract: A method is provided for designing an IC chip. The method includes receiving data from a pre-layout design process for the IC chip, routing a plurality of interconnecting wires to connect various devices of the IC chip, and extracting various circuit parameters. The method also includes simulating the IC chip using the extracted various circuit parameters to detect logic or timing error in the IC chip. The extracting the various circuit parameters includes establishing a statistical interconnect technology profile (ITP) file containing at least interconnect parasitic parameters based on correlations of interconnect layer geometric parameter variations.Type: GrantFiled: November 20, 2012Date of Patent: October 18, 2016Assignee: SHANGHAI IC R&D CENTER CO., LTDInventors: Zheng Ren, Shaojian Hu, Wei Zhou, Shoumian Chen, Yuhang Zhao
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Patent number: 9466699Abstract: A manufacturing method is provided for fabricating a vertical channel gate-all-around MOSFET by epitaxy processes. The method includes growing a first epitaxial layer on a top semiconducting layer of a substrate; etching the first epitaxial layer and the top layer to form a first source/drain pattern in the top layer; etching the first epitaxial layer to form a vertical channel structure; then forming a gate dielectric layer on the vertical channel structure surface; forming a sandwich structure composed of a bottom spacer layer, a gate electrode layer and a top spacer layer; etching the top spacer layer and the gate electrode layer to form a gate pattern followed by forming a top spacer structure thereon; growing a second epitaxial layer and etching to form a second source/drain pattern.Type: GrantFiled: July 18, 2014Date of Patent: October 11, 2016Assignee: SHANGHAI IC R&D CENTER CO., LTDInventors: Ao Guo, Zheng Ren, Shaojian Hu, Wei Zhou
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Publication number: 20160268396Abstract: A manufacturing method is provided for fabricating a vertical channel gate-all-around MOSFET by epitaxy processes. The method includes growing a first epitaxial layer on a top semiconducting layer of a substrate; etching the first epitaxial layer and the top layer to form a first source/drain pattern in the top layer; etching the first epitaxial layer to form a vertical channel structure; then forming a gate dielectric layer on the vertical channel structure surface; forming a sandwich structure composed of a bottom spacer layer, a gate electrode layer and a top spacer layer; etching the top spacer layer and the gate electrode layer to form a gate pattern followed by forming a top spacer structure thereon; growing a second epitaxial layer and etching to form a second source/drain pattern.Type: ApplicationFiled: July 18, 2014Publication date: September 15, 2016Inventors: Ao Guo, Zheng Ren, Shaojian Hu, Wei Zhou
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Publication number: 20160077299Abstract: A cable tray junction includes floor panel and a post secured to the floor panel. The post includes a splice plate connector defining a female coupling component. A splice plate interconnects the post and a cable tray. The splice plate includes a post connector, which defines a male coupling component received in the female coupling component to connect the splice plate to the post without the use of a separate fastener. The splice plate connector may have a curved groove and the post connector may have a tongue received in the curved groove. A wall panel connector of the post defines a wall panel groove in which a wall panel is received to connect the wall panel to the post.Type: ApplicationFiled: September 12, 2014Publication date: March 17, 2016Inventors: Brandon Michael Tally, Stephen Nathaniel Thompson, Zheng Ren
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Publication number: 20140351779Abstract: A method is provided for designing an IC chip. The method includes receiving data from a pre-layout design process for the IC chip, routing a plurality of interconnecting wires to connect various devices of the IC chip, and extracting various circuit parameters. The method also includes simulating the IC chip using the extracted various circuit parameters to detect logic or timing error in the IC chip. The extracting the various circuit parameters includes establishing a statistical interconnect technology profile (ITP) file containing at least interconnect parasitic parameters based on correlations of interconnect layer geometric parameter variations.Type: ApplicationFiled: November 20, 2012Publication date: November 27, 2014Inventors: Zheng Ren, Shaojian Hu, Wei Zhou, Shoumian Chen, Yuhang Zhao