Patents by Inventor Zheng Wu
Zheng Wu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10725668Abstract: A type of data relocation to perform on a group of solid state storage cells is selected from a group that includes garbage collection and wear leveling. Source blocks in the group of solid state storage cells are identified using the selected type of data relocation. The source blocks are read in order to obtain relocated data and the relocated data is stored in an open block in the group of solid state storage cells. Relocated data associated with the selected type of data relocation is stored in the open block and relocated data associated with the unselected type of data relocation is excluded from the open block.Type: GrantFiled: August 3, 2015Date of Patent: July 28, 2020Assignee: SK hynix Inc.Inventors: Xiangyu Tang, Jason Bellorado, Lingqi Zeng, Zheng Wu
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Publication number: 20200227302Abstract: A method for transferring a micro semiconductor element includes the following steps. A substrate, a bonding layer disposed on the substrate, and a supporting member disposed on the bonding layer opposite to the substrate are provided. The supporting member is bonded to a micro semiconductor element for supporting the same. A through hole is provided to extend through the substrate, the bonding layer, and the supporting member so as to forma transfer structure. A separation force is applied via the through hole to separate the micro semiconductor element from the supporting member.Type: ApplicationFiled: March 26, 2020Publication date: July 16, 2020Inventors: ZHENG WU, SHAO-YING TING, CHIA-EN LEE, CHEN-KE HSU
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Publication number: 20200220047Abstract: A micro-LED chip includes an epitaxial layered structure, and first and second electrodes. The epitaxial layered structure includes first-type and second-type semiconductor layers, and a light emitting layer sandwiched therebetween. The first and second electrodes are electrically connected to the first-type and second-type semiconductor layers, respectively. The micro-LED chip has a first distinctive region on an electrode surface of the first electrode. The first distinctive region has a surface morphology different from that of an adjacent region of the electrode surface of the first electrode. A method for manufacturing a micro-LED device including at least one micro-LED chip is also provided.Type: ApplicationFiled: March 13, 2020Publication date: July 9, 2020Inventors: Chia-En Lee, Chen-Ke Hsu, Zheng Wu
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Patent number: 10692527Abstract: An apparatus may include a circuit including a filter configured to update one or more adaptive coefficients of the filter based on an error signal. Further, the circuit may update a constrained coefficient of the filter based on the one or more adaptive coefficients, the constrained coefficient and a desired value. Moreover, the circuit may generate a sample of a sample sequence based on the one or more adaptive coefficients and the updated constrained coefficient, the error signal being based on the sample sequence.Type: GrantFiled: December 5, 2018Date of Patent: June 23, 2020Assignee: Seagate Technology LLCInventors: Jason Vincent Bellorado, Marcus Marrow, Zheng Wu
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Patent number: 10665256Abstract: An apparatus may include a circuit configured to receive a first phase control value of a phase control value signal, generate a first phase interpolator control signal value of a phase interpolator control signal and generate a first digital interpolator control signal value of a digital interpolator control signal. The apparatus may further be configured to phase interpolate a clock signal based on the first phase interpolator control signal value to produce a phase shifted clock signal and digitally interpolate a digital sample based on the first digital interpolator signal value to produce a phase shifted digital sample having an effective phase based on the first phase control value, the digital sample generated using the phase shifted clock signal as a sample clock.Type: GrantFiled: October 23, 2017Date of Patent: May 26, 2020Assignee: Seagate Technology LLCInventors: Jason Bellorado, Marcus Marrow, Zheng Wu
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Patent number: 10635844Abstract: Synthetic object detection data is generated for a modeled sensor, such as a camera. Scenario data specifying objects, such as vehicles, sensor intrinsics, such as focal length, principal point, and image size, and sensor extrinsics, such location and orientation in the scenario of the sensor, may be received. An object detector model may detect a given object in the scenario if it lies within the sensor's field of view, is large enough, and is not occluded. Two dimensional (2D) image plane position and velocity measurements may be generated. A measurement noise model may add noise to the measurements. Position, velocity, and measurement noise may be mapped into a three dimensional (3D) world coordinate system. An object detection list that includes time of detection, detected position and velocity, measurement accuracy, and an object classification for detected objects may be output.Type: GrantFiled: February 27, 2018Date of Patent: April 28, 2020Assignee: The MathWorks, Inc.Inventors: Trevor Roose, Vincent M. Pellissier, Witold R. Jachimczyk, Zheng Wu, Elad Kivelevitch, Gregory E. Dionne
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Patent number: 10615952Abstract: Provided are a synchronization method, a wide area system protection apparatus, a plant station and a computer readable storage medium. The method includes: sending to a second plant station a first data frame that includes a sequence number p and a sending timestamp of the first data frame; receiving a second data frame sent by the second plant station, and recording a receiving timestamp of the second data frame, the second data frame including a sequence number q of the second data frame, a sending timestamp of the second data frame and a receiving timestamp of the first data frame, and the first data frame being adjacent to the second frame on the second plant station; calculating a time phase difference and a crystal oscillator frequency deviation between the first plant station and the second plant station; and adjusting time and a clock frequency of the first plant station.Type: GrantFiled: May 10, 2019Date of Patent: April 7, 2020Assignees: STATE GRID JIANGSU ELECTRIC POWER CO., LTD., NARI TECHNOLOGY CO., LTD, NANJING CHSCOM ELECTRICAL TECHNOLOGY CO., LTD.Inventors: Jijun Yin, Qing Chen, Zheng Wu, Xiao Lu, Jianyu Luo, Haifeng Li, Xueming Li, Li Zhang, Feng Xue, Kaiming Luo, Lin Liu, Yunsong Yan, Jianfeng Ren, Haifeng Xia
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Patent number: 10608808Abstract: In certain embodiments, a method may include receiving one or more equalized samples of an input signal. The method may further include mitigating one or more excursions in the one or more equalized samples based on one or more current decisions of an iterative decoding process to generate compensated equalized samples. In addition, the method may include performing iterative decoding operations based on the compensated equalized samples, updating the current decisions of the iterative decoding process and outputting the current decisions as a converged result when the iterative decoding operations have converged for the compensated equalized samples.Type: GrantFiled: September 18, 2018Date of Patent: March 31, 2020Assignee: Seagate Technology LLCInventors: Jason Vincent Bellorado, Marcus Marrow, Zheng Wu
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Patent number: 10607648Abstract: Systems and methods are disclosed for head delay calibration and tracking multi-sensor magnetic recording (MSMR) systems. In certain embodiments, an apparatus may comprise a first reader and a second reader configured to simultaneously read from a single track of a data storage medium, the first reader offset from the second reader so that the first reader and the second reader detect a same signal pattern offset in time. The apparatus may further comprise a circuit configured to determine a relative offset between the first reader and the second reader, including setting a fixed delay for a first signal from the first reader, setting a second delay for a second signal from the second reader, and adjusting the second delay to align the second signal to the first signal using a timing loop, with the first signal used as a reference signal.Type: GrantFiled: July 2, 2018Date of Patent: March 31, 2020Assignee: Seagate Technology LLCInventors: Zheng Wu, Marcus Marrow, Jason Bellorado
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Publication number: 20200065262Abstract: Systems and methods are disclosed for full utilization of a data path's dynamic range. In certain embodiments, an apparatus may comprise a circuit including a first filter to digitally filter and output a first signal, a second filter to digitally filter and output a second signal, a summing node, and a first adaptation circuit. The summing node combine the first signal and the second signal to generate a combined signal at a summing node output. The first adaptation circuit may be configured to receive the combined signal, and filter the first signal and the second signal to set a dynamic amplitude range of the combined signal at the summing node output by modifying a first coefficient of the first filter and a second coefficient of the second filter based on the combined signal.Type: ApplicationFiled: November 4, 2019Publication date: February 27, 2020Applicant: Seagate Technology LLCInventors: Jason Bellorado, Marcus Marrow, Zheng Wu
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Patent number: 10561742Abstract: Methods for producing new neurons in the brain in vivo are provided according to aspects of the present invention which include introducing NeuroD1 into a glial cell, particularly into a reactive astrocyte or NG2 cell, thereby “converting” the reactive glial cell to a neuron. Methods of producing a neuronal phenotype in a glial cell are provided according to aspects of the present invention which include expressing exogenous NeuroD1 in the glial cell, wherein expressing exogenous NeuroD1 includes delivering an expression vector, such as a viral expression vector, including a nucleic acid encoding the exogenous NeuroD1 to the glial cell.Type: GrantFiled: July 19, 2013Date of Patent: February 18, 2020Assignee: The Penn State Research FoundationInventors: Gong Chen, Ziyuan Guo, Zheng Wu
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Patent number: 10559321Abstract: In one implementation, the disclosure provides a system including a first circuit to compute a timing error based on a received error signal and an estimated interference signal and a timing loop filter to output a frequency offset and a phase shift based on the timing error received as input. The system also includes a phase accumulator to accumulate at least a phase shift to generate a sample index and phase and an interpolation filter to generate samples of a side track signal using the sample index and phase.Type: GrantFiled: February 13, 2019Date of Patent: February 11, 2020Assignee: SEAGATE TECHNOLOGY LLCInventors: Zheng Wu, Jason Bellorado, Marcus Marrow, Vincent B Ashe
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Publication number: 20200005819Abstract: An apparatus may include a circuit configured to receive first and second samples of an underlying data from respective first and second sample periods and which correspond to respective first and second sensors, a phase control value may have first and second values during respective first and second sample periods. The phase control value may be a control value for a sample clock signal. The circuit may also determine a difference in the phase control value between the first value and the second value. The circuit may then digitally interpolate the first and second samples to produce a phase shifted first and second samples where the digital interpolation of at least one of the first and second samples mat be at least in part based on the difference in the phase control value to compensate for a phase misalignment between the first sample and the second sample.Type: ApplicationFiled: September 13, 2019Publication date: January 2, 2020Inventors: Jason Bellorado, Marcus Marrow, Zheng Wu
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Publication number: 20190384879Abstract: Provided are a method and apparatus for estimating a meteorology sensitive load power. The method includes: obtaining a meteorology sensitive load power estimation model; inputting a daily load curve of a date to be estimated to the meteorology sensitive load power estimation model and extracting a daily load curve dimension reduction feature of the date to be estimated; and outputting a meteorology sensitive load power based on the daily load curve dimension reduction feature of the date to be estimated and mapping relationships from daily load curve dimension reduction features onto meteorology sensitive load powers. The proposed estimation model can directly obtain the meteorology sensitive load power curve from the daily load curve, and is especially applicable to cases where meteorology data is frequently lost in practical applications.Type: ApplicationFiled: June 13, 2019Publication date: December 19, 2019Applicants: STATE GRID JIANGSU ELECTRIC POWER CO., LTD., STATE GRID CORPORATION OF CHINA, STATE GRID JIANGSU ELECTRIC POWER COMPANY RESEARCH INSTITUTE, HOHAI UNIVERSITYInventors: Jijun Yin, Qing Chen, Zheng Wu, Xiao Lu, Jianyu Luo, Lin Liu, Jingbo Zhao, Ping Ju, Yanxiang Chen, Chuan Qin, Jiajun Shi, Shiwu Liao, Xinyao Zhu, Dajiang Wang
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Patent number: 10496559Abstract: Systems and methods are disclosed for full utilization of a data path's dynamic range. In certain embodiments, an apparatus may comprise a circuit including a first filter to digitally filter and output a first signal, a second filter to digitally filter and output a second signal, a summing node, and a first adaptation circuit. The summing node combine the first signal and the second signal to generate a combined signal at a summing node output. The first adaptation circuit may be configured to receive the combined signal, and filter the first signal and the second signal to set a dynamic amplitude range of the combined signal at the summing node output by modifying a first coefficient of the first filter and a second coefficient of the second filter based on the combined signal.Type: GrantFiled: October 10, 2017Date of Patent: December 3, 2019Assignee: Seagate Technology LLCInventors: Jason Bellorado, Marcus Marrow, Zheng Wu
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Patent number: 10483999Abstract: An apparatus may include a circuit configured to generate, by an analog to digital converter (ADC), one or more ADC samples based on an input signal. The circuit may be further configured to generate a first estimated signal using a first channel pulse response estimation with a gain constraint based on the one or more ADC samples and generate a second estimated signal using a second channel pulse response estimation with a phase constraint based on the one or more ADC samples.Type: GrantFiled: June 4, 2018Date of Patent: November 19, 2019Assignee: Seagate Technology LLCInventors: Zheng Wu, Jason Vincent Bellorado, Marcus Marrow
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Patent number: 10468060Abstract: An apparatus may comprise a circuit configured to receive first underlying data corresponding to a first signal and receive a second signal corresponding to second underlying data. The circuit may determine an interference component signal based on the first underlying data corresponding to the first signal and a first channel pulse response shape for the first signal, determine estimated decisions corresponding to the second signal based on the second signal, and determine an estimated signal based on the estimated decisions corresponding to the second signal and a second channel pulse response shape for the second signal. The circuit may then generate a remaining signal based on the estimated signal and the second signal, generate an error signal based on the interference component signal and the remaining signal, and adapt one or more parameters of the first channel pulse response shape based on the error signal.Type: GrantFiled: September 27, 2018Date of Patent: November 5, 2019Assignee: Seagate Technology LLCInventors: Zheng Wu, Jason Bellorado, Marcus Marrow, Vincent Brendan Ashe
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Patent number: 10460762Abstract: An apparatus may comprise a circuit configured to receive first underlying data corresponding to a first signal with a first rate and receive a second signal with a second rate corresponding to second underlying data. The circuit may interpolate the first underlying data to generate a plurality of interpolated signals, determine, for the first signal, a first channel pulse response shape with the first rate, and determine an interference component signal based on the plurality of interpolated signals and the first channel pulse response shape. The circuit may then cancel interference in the second signal using the interference component signal to generate a cleaned signal.Type: GrantFiled: September 4, 2018Date of Patent: October 29, 2019Assignee: Seagate Technology LLCInventors: Zheng Wu, Jason Bellorado, Marcus Marrow, Vincent Brendan Ashe
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Patent number: 10410672Abstract: Systems and methods are disclosed for applying multi-stage multiple input single output (MISO) circuits for fast adaptation. An apparatus may comprise a first reader and a second reader configured to simultaneously read from a single track of a data storage medium, a MISO circuit. The MISO circuit may include a first stage filter having a first number of taps and configured to filter signal samples received from the first reader and the second reader and produce first filtered samples. The MISO circuit may also include a second stage filter having a second number of taps greater than the first number, and be configured to receive the first filtered samples corresponding to the first reader and the second reader from the first filter stage, filter the first filtered samples to produce second filtered samples, and combine the second filtered samples to produce a combined sample output.Type: GrantFiled: August 19, 2018Date of Patent: September 10, 2019Assignee: Seagate Technology LLCInventors: Marcus Marrow, Jason Bellorado, Zheng Wu
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Patent number: 10394004Abstract: An optical system may include a lens assembly that has two or more single-sided wafer level optics (WLO) lenses arranged to propagate light. The optical system can further include an image sensor, wherein the lens assembly is arranged relative to the image sensor to propagate light received at a first surface of the lens assembly, through the two or more single-sided WLO lenses and to the image sensor. In some embodiments, the optical system further includes a camera which includes the lens assembly and the image sensor. In various embodiments, a smart phone, a tablet computer, or another mobile computing device may include such a camera. In some embodiments, the at least two single-sided wafer level optics (WLO) lenses are each separated by a gap G, wherein the gap may be different between each of the single-sided lenses, and the gap G may be zero.Type: GrantFiled: September 23, 2016Date of Patent: August 27, 2019Assignee: QUALCOMM IncorporatedInventors: Todor Georgiev Georgiev, Wen-Yu Sun, Zheng-wu Li, Jon Lasiter