Abstract: A detecting circuit includes a network interface, a switch, a baseboard management controller (BMC) having first and second signal pins, and a detecting unit. The first and second signal pins receive low level signals when the network line is disconnected from the network interface. The first signal pin receives a high level signal and the second signal pin receives a low level signal when the network line is connected to the network interface but the network card is malfunctioning. The first and second signal pins receive high level signals when the network line is connected to the network interface and the network card works normally.

Abstract: A system is used for acquiring Basic Input/Output System (BIOS) debug codes. The system includes a platform controller hub (PCH), a storage chip, and a baseboard management controller (BMC). The PCH reads power-on self tests (POST) codes from an address port of a bus, and converts the POST codes to binary data and stores the binary data in the storage chip. The BMC reads the binary data stored in the storage chip and defines the binary data as virtual sensor data, which conform with threshold type data, and decodes the virtual sensor data to POST codes and controls a display unit to display the POST codes.

Abstract: A connection system includes a keyboard-video-mouse (KVM) device, first and second electronic devices, first and second cables. The first cable includes a first terminal connected to the KVM device, a second terminal connected to the first electronic device, and a first indicator positioned on the first cable and close to the second terminal. The second cable includes a third terminal connected to the KVM device, a fourth terminal connected to the second electronic device, and a second indicator positioned on the second cable and close to the fourth terminal. The KVM device includes first to third switches, and a logic circuit connected to the first to third switches and the first and second indicators. When the first and second switches are closed, the first indicator is lit by the logic circuit. When the first and third switches are closed, the second indicator is lit by the logic circuit.

Abstract: An electronic device includes an internal storage module, a baseboard management controller (BMC) and a port. The internal storage module stores a first firmware and a boot application. The port connects to an external storage for storing a second firmware which is a backup of the first firmware. After the electronic device is powered on, the BMC runs the boot application to load the first firmware from the internal storage module. If the first firmware fails to load, the BMC copies the second firmware from the external storage to the internal storage module to replace the first firmware.

Abstract: A detecting circuit includes a network interface, a switch, a baseboard management controller (BMC) having first and second signal pins, and a detecting unit. The first and second signal pins receive low level signals when the network line is disconnected from the network interface. The first signal pin receives a high level signal and the second signal pin receives a low level signal when the network line is connected to the network interface but the network card is malfunctioning. The first and second signal pins receive high level signals when the network line is connected to the network interface and the network card works normally.

Abstract: A system is used for acquiring Basic Input/Output System (BIOS) debug codes. The system includes a platform controller hub (PCH), a storage chip, and a baseboard management controller (BMC). The PCH reads power-on self tests (POST) codes from an address port of a bus, and converts the POST codes to binary data and stores the binary data in the storage chip. The BMC reads the binary data stored in the storage chip and defines the binary data as virtual sensor data, which conform with threshold type data, and decodes the virtual sensor data to POST codes and controls a display unit to display the POST codes.

Abstract: A male connector includes a main body, a plug extending from an end of the main body, and two elastic members attached to opposite sides of the main body. An end of each of the elastic members is secured to the main body near the end thereof, and the remaining portion of each of the elastic members is cantilevered towards an opposite end of the main body. Each of the elastic members includes a locking portion attached thereto configured for engaging with a female connector.