Patents by Inventor Zheng-Yi Lim
Zheng-Yi Lim has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10840212Abstract: A method includes aligning a first electrical connector of a first package component to a second electrical connector of a second package component. With the first electrical connector aligned to the second electrical connector, a metal layer is plated on the first and the second electrical connectors. The metal layer bonds the first electrical connector to the second electrical connector.Type: GrantFiled: September 24, 2019Date of Patent: November 17, 2020Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Zheng-Yi Lim, Yi-Wen Wu, Tzong-Hann Yang, Ming-Che Ho, Chung-Shi Liu
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Publication number: 20200020662Abstract: A method includes aligning a first electrical connector of a first package component to a second electrical connector of a second package component. With the first electrical connector aligned to the second electrical connector, a metal layer is plated on the first and the second electrical connectors. The metal layer bonds the first electrical connector to the second electrical connector.Type: ApplicationFiled: September 24, 2019Publication date: January 16, 2020Inventors: Zheng-Yi Lim, Yi-Wen Wu, Tzong-Hann Yang, Ming-Che Ho, Chung-Shi Liu
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Patent number: 10483230Abstract: A method includes aligning a first electrical connector of a first package component to a second electrical connector of a second package component. With the first electrical connector aligned to the second electrical connector, a metal layer is plated on the first and the second electrical connectors. The metal layer bonds the first electrical connector to the second electrical connector.Type: GrantFiled: June 26, 2017Date of Patent: November 19, 2019Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Zheng-Yi Lim, Yi-Wen Wu, Tzong-Hann Yang, Ming-Che Ho, Chung-Shi Liu
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Patent number: 9953891Abstract: A method includes coating a passivation layer overlying a semiconductor substrate and forming an interconnect layer overlying the passivation layer. The interconnect layer includes a line region and a landing pad region. The method further includes forming a metallic layer including tin on a surface of the interconnect layer using an immersion process, forming a protective layer on the metallic layer, and exposing a portion of the metallic layer on the landing pad region of the interconnect layer through the protective layer.Type: GrantFiled: July 23, 2015Date of Patent: April 24, 2018Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Yi-Wen Wu, Zheng-Yi Lim, Ming-Che Ho, Chung-Shi Liu
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Publication number: 20170294402Abstract: A method includes aligning a first electrical connector of a first package component to a second electrical connector of a second package component. With the first electrical connector aligned to the second electrical connector, a metal layer is plated on the first and the second electrical connectors. The metal layer bonds the first electrical connector to the second electrical connector.Type: ApplicationFiled: June 26, 2017Publication date: October 12, 2017Inventors: Zheng-Yi Lim, Yi-Wen Wu, Tzong-Hann Yang, Ming-Che Ho, Chung-Shi Liu
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Patent number: 9691738Abstract: A method includes aligning a first electrical connector of a first package component to a second electrical connector of a second package component. With the first electrical connector aligned to the second electrical connector, a metal layer is plated on the first and the second electrical connectors. The metal layer bonds the first electrical connector to the second electrical connector.Type: GrantFiled: August 24, 2015Date of Patent: June 27, 2017Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Zheng-Yi Lim, Yi-Wen Wu, Tzong-Hann Yang, Ming-Che Ho, Chung-Shi Liu
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Patent number: 9275965Abstract: A method of forming an integrated circuit device comprises forming a metal pillar over a semiconductor substrate. The method also comprises forming a solder layer over the metal pillar. The method further comprises forming a metallization layer comprising a cobalt (Co) element, the metallization layer covering the metal pillar and the solder layer. The method additionally comprises thermally reflowing the solder layer to form a solder bump, driving the Co element of the metallization layer into the solder bump. The method also comprises oxidizing the metallization layer to form a metal oxide layer on a sidewall surface of the metal pillar.Type: GrantFiled: July 25, 2014Date of Patent: March 1, 2016Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chien Ling Hwang, Zheng-Yi Lim, Chung-Shi Liu
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Publication number: 20150364449Abstract: A method includes aligning a first electrical connector of a first package component to a second electrical connector of a second package component. With the first electrical connector aligned to the second electrical connector, a metal layer is plated on the first and the second electrical connectors. The metal layer bonds the first electrical connector to the second electrical connector.Type: ApplicationFiled: August 24, 2015Publication date: December 17, 2015Inventors: Zheng-Yi Lim, Yi-Wen Wu, Tzong-Hann Yang, Ming-Che Ho, Chung-Shi Liu
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Publication number: 20150325539Abstract: A method includes coating a passivation layer overlying a semiconductor substrate and forming an interconnect layer overlying the passivation layer. The interconnect layer includes a line region and a landing pad region. The method further includes forming a metallic layer including tin on a surface of the interconnect layer using an immersion process, forming a protective layer on the metallic layer, and exposing a portion of the metallic layer on the landing pad region of the interconnect layer through the protective layer.Type: ApplicationFiled: July 23, 2015Publication date: November 12, 2015Inventors: Yi-Wen WU, Zheng-Yi LIM, Ming-Che HO, Chung-Shi LIU
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Patent number: 9117772Abstract: A method includes aligning a first electrical connector of a first package component to a second electrical connector of a second package component. With the first electrical connector aligned to the second electrical connector, a metal layer is plated on the first and the second electrical connectors. The metal layer bonds the first electrical connector to the second electrical connector.Type: GrantFiled: June 19, 2012Date of Patent: August 25, 2015Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Zheng-Yi Lim, Yi-Wen Wu, Tzong-Hann Yang, Ming-Che Ho, Chung-Shi Liu
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Patent number: 9099396Abstract: A semiconductor device includes a conductive layer formed on the surface of a post-passivation interconnect (PPI) structure by an immersion tin process. A polymer layer is formed on the conductive layer and patterned with an opening to expose a portion of the conductive layer. A solder bump is then formed in the opening of the polymer layer to electrically connect to the PPI structure.Type: GrantFiled: November 8, 2011Date of Patent: August 4, 2015Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Yi-Wen Wu, Zheng-Yi Lim, Ming-Che Ho, Chung-Shi Liu
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Patent number: 9048135Abstract: An integrated circuit device includes a Cu pillar and a solder layer overlying the Cu pillar. A Co-containing metallization layer is formed to cover the Cu pillar and the solder layer, and then a thermally reflow process is performed to form a solder bump and drive the Co element into the solder bump. Next, an oxidation process is performed to form a cobalt oxide layer on the sidewall surface of the Cu pillar.Type: GrantFiled: February 16, 2011Date of Patent: June 2, 2015Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chien Ling Hwang, Zheng-Yi Lim, Chung-Shi Liu
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Publication number: 20140342546Abstract: A method of forming an integrated circuit device comprises forming a metal pillar over a semiconductor substrate. The method also comprises forming a solder layer over the metal pillar. The method further comprises forming a metallization layer comprising a cobalt (Co) element, the metallization layer covering the metal pillar and the solder layer. The method additionally comprises thermally reflowing the solder layer to form a solder bump, driving the Co element of the metallization layer into the solder bump. The method also comprises oxidizing the metallization layer to form a metal oxide layer on a sidewall surface of the metal pillar.Type: ApplicationFiled: July 25, 2014Publication date: November 20, 2014Inventors: Chien Ling HWANG, Zheng-Yi LIM, Chung-Shi LIU
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Patent number: 8865586Abstract: A method includes forming a polymer layer over a metal pad, forming an opening in the polymer layer to expose a portion of the metal pad, and forming an under-bump-metallurgy (UBM). The UBM includes a portion extending into the opening to electrically couple to the metal pad.Type: GrantFiled: January 5, 2012Date of Patent: October 21, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yi-Wen Wu, Zheng-Yi Lim, Ming-Che Ho, Chung-Shi Liu
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Publication number: 20130334692Abstract: A method includes aligning a first electrical connector of a first package component to a second electrical connector of a second package component. With the first electrical connector aligned to the second electrical connector, a metal layer is plated on the first and the second electrical connectors. The metal layer bonds the first electrical connector to the second electrical connector.Type: ApplicationFiled: June 19, 2012Publication date: December 19, 2013Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Zheng-Yi Lim, Yi-Wen Wu, Tzong-Hann Yang, Ming-Che Ho, Chung-Shi Liu
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Patent number: 8501615Abstract: A system and method for forming metal bumps is provided. An embodiment comprises attaching conductive material to a carrier medium and then contacting the conductive material to conductive regions of a substrate. Portions of the conductive material are then bonded to the conductive regions using a bonding process to form conductive caps on the conductive regions, and residual conductive material and the carrier medium are removed. A reflow process is used to reflow the conductive caps into conductive bumps.Type: GrantFiled: June 15, 2011Date of Patent: August 6, 2013Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ming-Da Cheng, Chih-Wei Lin, Hsiu-Jen Lin, Tzong-Hann Yang, Wen-Hsiung Lu, Zheng-Yi Lim, Yi-Wen Wu, Chung-Shi Liu
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Publication number: 20130175685Abstract: A method includes forming a polymer layer over a metal pad, forming an opening in the polymer layer to expose a portion of the metal pad, and forming an under-bump-metallurgy (UBM). The UBM includes a portion extending into the opening to electrically couple to the metal pad.Type: ApplicationFiled: January 5, 2012Publication date: July 11, 2013Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yi-Wen Wu, Zheng-Yi Lim, Ming-Che Ho, Chung-Shi Liu
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Publication number: 20130113094Abstract: A semiconductor device includes a conductive layer formed on the surface of a post-passivation interconnect (PPI) structure by an immersion tin process. A polymer layer is formed on the conductive layer and patterned with an opening to expose a portion of the conductive layer. A solder bump is then formed in the opening of the polymer layer to electrically connect to the PPI structure.Type: ApplicationFiled: November 8, 2011Publication date: May 9, 2013Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Yi-Wen WU, Zheng-Yi LIM, Ming-Che HO, Chung-Shi LIU
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Publication number: 20120322255Abstract: A system and method for forming metal bumps is provided. An embodiment comprises attaching conductive material to a carrier medium and then contacting the conductive material to conductive regions of a substrate. Portions of the conductive material are then bonded to the conductive regions using a bonding process to form conductive caps on the conductive regions, and residual conductive material and the carrier medium are removed. A reflow process is used to reflow the conductive caps into conductive bumps.Type: ApplicationFiled: June 15, 2011Publication date: December 20, 2012Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ming-Da Cheng, Chih-Wei Lin, Hsiu-Jen Lin, Tzong-Hann Yang, Wen-Hsiung Lu, Zheng-Yi Lim, Yi-Wen Wu, Chung-Shi Liu
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Publication number: 20120286423Abstract: A method of forming a device includes providing a substrate, and forming a solder bump over the substrate. A minor element is introduced to a region adjacent a top surface of the solder bump. A re-flow process is then performed to the solder bump to drive the minor element into the solder bump.Type: ApplicationFiled: July 23, 2012Publication date: November 15, 2012Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Ming-Da Cheng, Ming-Che Ho, Chung-Shi Liu, Chien Ling Hwang, Cheng-Chung Lin, Hui-Jung Tsai, Zheng-Yi Lim