Abstract: An integrated circuit (IC) chip with polish stop layers and a method of fabricating the IC chip are disclosed. The method includes forming a first IC chip having a device region and a peripheral region. Forming the first IC chip includes forming a device layer on a substrate, forming an interconnect structure on the device layer, depositing a first dielectric layer on a first portion of the interconnect structure in the peripheral region, depositing a second dielectric layer on the first dielectric layer and on a second portion of the interconnect structure in the device region, and performing a polishing process on the second dielectric layer to substantially coplanarize a top surface of the second dielectric layer with a top surface of the first dielectric layer. The method further includes performing a bonding process on the second dielectric layer to bond a second IC chip to the first IC chip.

Abstract: An integrated circuit die with two material layers having metal nano-particles and the method of forming the same are provided. The integrated circuit die includes a device layer comprising a first transistor, a first interconnect structure on a first side of the device layer, a first material layer on the first interconnect structure, wherein the first material layer comprises first metal nano-particles, and a second material layer bonded to the first material layer, wherein the second material layer comprises second metal nano-particles, and wherein the first material layer and the second material layer share an interface.

Abstract: Provided is a method of forming a semiconductor structure including: bonding a device wafer onto a carrier wafer; forming a support structure between an edge of the device wafer and an edge of the carrier wafer, wherein the support structure surrounds a device layer of the device wafer along a closed path; removing a substrate and a portion of a bonding dielectric layer of the device wafer from a backside of the device wafer to expose the support structures while the support structure is in place; and removing the support structure through an acid etchant.

Abstract: A semiconductor structure and a manufacturing method thereof are provided. A semiconductor structure includes a first nitride-containing layer on a side of a carrier substrate, first semiconductor devices thermally coupled to the first nitride-containing layer, a first interconnect structure physically and electrically coupled to first sides of the first semiconductor devices, and a first metal-containing dielectric layer bonding the first nitride-containing layer to the first interconnect structure. A thermal conductivity of the first nitride-containing layer is greater than a thermal conductivity of the first metal-containing dielectric layer.

Abstract: A carrier structure and methods of forming and using the same are described. In some embodiments, the method includes forming one or more devices over a substrate, forming a first interconnect structure over the one or more devices, and bonding the first interconnect structure to a carrier structure. The carrier structure includes a semiconductor substrate, a release layer, and a first dielectric layer, and the release layer includes a metal nitride. The method further includes flipping over the one or more devices so the carrier structure is located at a bottom, performing backside processes, flipping over the one or more devices so the carrier structure is located at a top, and exposing the carrier structure to IR lights. Portions of the release layer are separated from the first dielectric layer.

Abstract: The present disclosure describes a method of forming low thermal budget dielectrics in semiconductor devices.

Abstract: The present disclosure describes a method of forming low thermal budget dielectrics in semiconductor devices. The method includes forming, on a substrate, first and second fin structures with an opening in between, filling the opening with a flowable isolation material, treating the flowable isolation material with a plasma, and removing a portion of the plasma-treated flowable isolation material between the first and second fin structures.

Abstract: A method for manufacturing a semiconductor structure includes: forming a first bonding layer on a device substrate formed with a semiconductor device so as to cover the semiconductor device, wherein the first bonding layer includes a first metal oxide material in an amorphous state; forming a second bonding layer on a carrier substrate, wherein the second bonding layer includes a second metal oxide material in an amorphous state; conducting a surface modification process on the first bonding layer and the second bonding layer; bonding the device substrate and the carrier substrate to each other through the first and second bonding layers; and annealing the first and second bonding layers so as to convert the first and second metal oxide materials from the amorphous state to a crystalline state.

Abstract: The present disclosure describes a method to form a bonded semiconductor structure. The method includes forming a first bonding layer on a first wafer, forming a debonding structure on a second wafer, forming a second bonding layer on the debonding structure, bonding the first and second wafers with the first and second bonding layers, and debonding the second wafer from the first wafer via the debonding structure. The debonding structure includes a first barrier layer, a second barrier layer, and a water-containing dielectric layer between the first and second barrier layers.

Abstract: The present disclosure describes a method of forming low thermal budget dielectrics in semiconductor devices.

Abstract: An atomic layer deposition method is provided. The atomic layer deposition method includes the following steps. A substrate is placed in a reaction chamber. At least one deposition cycle is performed to deposit a metal film on the substrate. The at least one deposition cycle includes the following steps. A metal precursor is introduced in the reaction chamber. A hydrogen plasma is introduced to be reacted with the metal precursor adsorbed on the substrate to form the metal film. An annealing process is performed on the metal film. The at least one deposition cycle is performed in a hydrogen atmosphere under UV light irradiation.

Abstract: An atomic layer deposition method is provided. The atomic layer deposition method includes the following steps. A substrate is placed in a reaction chamber. At least one deposition cycle is performed to deposit a metal film on the substrate. The at least one deposition cycle includes the following steps. A metal precursor is introduced in the reaction chamber. A hydrogen plasma is introduced to be reacted with the metal precursor adsorbed on the substrate to form the metal film. An annealing process is performed on the metal film. The at least one deposition cycle is performed in a hydrogen atmosphere under UV light irradiation.

Abstract: A semiconductor interconnect structure and a manufacturing method thereof are provided. The semiconductor interconnect structure includes a barrier metal layer, a copper metal layer, and a compound thin film. The barrier metal layer is formed on an interconnect trench, the copper metal layer is formed on the barrier metal layer, and the compound thin film is formed on a surface of the copper metal layer, wherein the compound thin film contains organocopper and amorphous carbon. Therefore, the resulting semiconductor interconnect structure has reduced resistivity.