Patents by Inventor Zheng-Yong Liang
Zheng-Yong Liang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240355733Abstract: A semiconductor structure and a manufacturing method thereof are provided. A semiconductor structure includes a first nitride-containing layer on a side of a carrier substrate, first semiconductor devices thermally coupled to the first nitride-containing layer, a first interconnect structure physically and electrically coupled to first sides of the first semiconductor devices, and a first metal-containing dielectric layer bonding the first nitride-containing layer to the first interconnect structure. A thermal conductivity of the first nitride-containing layer is greater than a thermal conductivity of the first metal-containing dielectric layer.Type: ApplicationFiled: April 20, 2023Publication date: October 24, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Zheng-Yong Liang, Wei-Ting Yeh, Yu-Yun Peng, Keng-Chu Lin
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Publication number: 20240355805Abstract: Provided is a method of forming a semiconductor structure including: bonding a device wafer onto a carrier wafer; forming a support structure between an edge of the device wafer and an edge of the carrier wafer, wherein the support structure surrounds a device layer of the device wafer along a closed path; removing a substrate and a portion of a bonding dielectric layer of the device wafer from a backside of the device wafer to expose the support structures while the support structure is in place; and removing the support structure through an acid etchant.Type: ApplicationFiled: April 21, 2023Publication date: October 24, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Wei-Ting Yeh, Zheng-Yong Liang, Yu-Yun Peng, Keng-Chu Lin
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Publication number: 20240282761Abstract: A carrier structure and methods of forming and using the same are described. In some embodiments, the method includes forming one or more devices over a substrate, forming a first interconnect structure over the one or more devices, and bonding the first interconnect structure to a carrier structure. The carrier structure includes a semiconductor substrate, a release layer, and a first dielectric layer, and the release layer includes a metal nitride. The method further includes flipping over the one or more devices so the carrier structure is located at a bottom, performing backside processes, flipping over the one or more devices so the carrier structure is located at a top, and exposing the carrier structure to IR lights. Portions of the release layer are separated from the first dielectric layer.Type: ApplicationFiled: February 22, 2023Publication date: August 22, 2024Inventors: Zheng Yong Liang, Wei-Ting Yeh, Jyh-Cherng Sheu, Yu-Yun Peng, Keng-Chu Lin
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Publication number: 20240170323Abstract: The present disclosure describes a method of forming low thermal budget dielectrics in semiconductor devices.Type: ApplicationFiled: January 30, 2024Publication date: May 23, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Mrunal Abhijith KHADERBAD, Ko-Feng Chen, Zheng-Yong Liang, Chen-Han Wang, De-Yang Chiou, Yu-Yun Peng, Keng-Chu Lin
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Patent number: 11942358Abstract: The present disclosure describes a method of forming low thermal budget dielectrics in semiconductor devices. The method includes forming, on a substrate, first and second fin structures with an opening in between, filling the opening with a flowable isolation material, treating the flowable isolation material with a plasma, and removing a portion of the plasma-treated flowable isolation material between the first and second fin structures.Type: GrantFiled: March 12, 2021Date of Patent: March 26, 2024Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Mrunal Abhijith Khaderbad, Ko-Feng Chen, Zheng-Yong Liang, Chen-Han Wang, De-Yang Chiou, Yu-Yun Peng, Keng-Chu Lin
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Publication number: 20240030180Abstract: A method for manufacturing a semiconductor structure includes: forming a first bonding layer on a device substrate formed with a semiconductor device so as to cover the semiconductor device, wherein the first bonding layer includes a first metal oxide material in an amorphous state; forming a second bonding layer on a carrier substrate, wherein the second bonding layer includes a second metal oxide material in an amorphous state; conducting a surface modification process on the first bonding layer and the second bonding layer; bonding the device substrate and the carrier substrate to each other through the first and second bonding layers; and annealing the first and second bonding layers so as to convert the first and second metal oxide materials from the amorphous state to a crystalline state.Type: ApplicationFiled: July 20, 2022Publication date: January 25, 2024Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Zheng-Yong LIANG, Wei-Ting YEH, Yu-Yun PENG, Keng-Chu LIN
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Publication number: 20220415696Abstract: The present disclosure describes a method to form a bonded semiconductor structure. The method includes forming a first bonding layer on a first wafer, forming a debonding structure on a second wafer, forming a second bonding layer on the debonding structure, bonding the first and second wafers with the first and second bonding layers, and debonding the second wafer from the first wafer via the debonding structure. The debonding structure includes a first barrier layer, a second barrier layer, and a water-containing dielectric layer between the first and second barrier layers.Type: ApplicationFiled: March 23, 2022Publication date: December 29, 2022Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Wei-Ting YEH, Zheng Yong Liang, De-Yang Chiou, Yu-Yun Peng, Keng-Chu Lin
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Publication number: 20220293458Abstract: The present disclosure describes a method of forming low thermal budget dielectrics in semiconductor devices.Type: ApplicationFiled: March 12, 2021Publication date: September 15, 2022Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Mrunal Abhijith Khaderbad, Ko-Feng Chen, Zheng Yong Liang, Chen-Han Wang, De-Yang Chiou, Yu-Yun Peng, Keng-Chu Lin
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Patent number: 10522361Abstract: An atomic layer deposition method is provided. The atomic layer deposition method includes the following steps. A substrate is placed in a reaction chamber. At least one deposition cycle is performed to deposit a metal film on the substrate. The at least one deposition cycle includes the following steps. A metal precursor is introduced in the reaction chamber. A hydrogen plasma is introduced to be reacted with the metal precursor adsorbed on the substrate to form the metal film. An annealing process is performed on the metal film. The at least one deposition cycle is performed in a hydrogen atmosphere under UV light irradiation.Type: GrantFiled: August 21, 2018Date of Patent: December 31, 2019Assignee: National Tsing Hua UniversityInventors: Zheng-Yong Liang, Chao-Hui Yeh, Jui-Hsiung Liu, Po-Wen Chiu
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Publication number: 20190362979Abstract: An atomic layer deposition method is provided. The atomic layer deposition method includes the following steps. A substrate is placed in a reaction chamber. At least one deposition cycle is performed to deposit a metal film on the substrate. The at least one deposition cycle includes the following steps. A metal precursor is introduced in the reaction chamber. A hydrogen plasma is introduced to be reacted with the metal precursor adsorbed on the substrate to form the metal film. An annealing process is performed on the metal film. The at least one deposition cycle is performed in a hydrogen atmosphere under UV light irradiation.Type: ApplicationFiled: August 21, 2018Publication date: November 28, 2019Applicant: National Tsing Hua UniversityInventors: Zheng-Yong Liang, Chao-Hui Yeh, Jui-Hsiung Liu, Po-Wen Chiu
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Publication number: 20170025360Abstract: A semiconductor interconnect structure and a manufacturing method thereof are provided. The semiconductor interconnect structure includes a barrier metal layer, a copper metal layer, and a compound thin film. The barrier metal layer is formed on an interconnect trench, the copper metal layer is formed on the barrier metal layer, and the compound thin film is formed on a surface of the copper metal layer, wherein the compound thin film contains organocopper and amorphous carbon. Therefore, the resulting semiconductor interconnect structure has reduced resistivity.Type: ApplicationFiled: September 10, 2015Publication date: January 26, 2017Inventors: Zheng-Yong Liang, Chao-Hui Yeh, Po-Wen Chiu