Abstract: Disclosed are an agarase mutant with improved thermal stability and application thereof, belonging to the fields of genetic engineering technology and enzyme engineering. The present disclosure provides an agarase mutant, which is obtained by mutating the amino acid at the 86th site, the 373rd site, the 374th site, the 496th site, the 507th site, or the 747th site of agarase with an amino acid sequence as shown in SEQ ID NO. 1. The agarase mutant provided by the present disclosure improves the thermal stability and the hydrolytic activity of the agarase. Compared with the wild type enzyme, the mutant enzyme shows excellent heat resistance and can be industrially used at a relatively high temperature, so that the utilization rate of agar raw materials and the yield of oligosaccharides from agar are improved, and the mutant enzyme has a good industrial application prospect.

Abstract: A method for preparing V-type porous starch includes: mixing starch and a first ethanol solution in a reaction kettle, adding concentrated hydrochloric acid to the reaction kettle for acidity regulation, and controlling a temperature of a reaction system in the reaction kettle at 80-150° C.; cooling the reaction kettle, and adding a sodium hydroxide solution to the reaction system in the reaction kettle, until a pH of a mixture in the reaction kettle is neutral, to yield a starch solution; and centrifuging the starch solution, washing a collected precipitate with a second ethanol solution, leaching, drying, cooling, and pulverizing, to yield V-type porous starch.

Abstract: A method for reducing latency and increasing throughput in a reconfigurable computing system includes receiving a compute graph for execution on a reconfigurable dataflow processor comprising a grid of compute units and grid of memory units interconnected with a switching array. The compute graph includes a node specifying an operation on a tensor. The node may be split into multiple nodes that each specify the operation on a distinctive portion of the tensor to produce a first modified compute graph. The first modified compute graph may be executed. In addition, the multiple nodes may be within a single meta-pipeline stage and may be processed in parallel. Furthermore, the compute graph may further comprise a separate node for gathering the distinctive portions of the tensor into a complete tensor, to produce a second modified compute graph.

Abstract: Systems formed by a multi-bit three-transistor (3T) memory cell (i.e., dynamic-analog RAM) are provided. The 3T memory cell includes: a read-access transistor M1 in electrical communication with a read bitline; a switch transistor M2 in electrical communication with the read-access transistor M1; a write-access transistor M3 in electrical communication with the read-access transistor M1 and a write bitline; and a memory node MEM in electrical communication between the read-access transistor M1 and the write-access transistor M3, wherein the memory node MEM is configured to store a 4-bit weight WE. An array of the 3T memory cells (i.e., dynamic-analog RAMs) may form a computing-in-memory (CIM) macro, and further form a convolutional neural network (CNN) accelerator by communicating with an application-specific integrated circuit (ASIC) which communicates with a global weight static random access memory and an activation static random access memory.

Abstract: There are provided solutions for multiagent debate. In a method, a first and a second response representation are determined by a first and a second agent in a plurality of agents based on a first query representation for a query in a natural language, respectively, and the first and second response representations are convertible to a first and a second answer to the query in the natural language, respectively. A second query representation is obtained based on the first query representation, and at least one of the first and second response representations. A response representation is determined based on the second query representation by at least one of the first and second agents, and the response representation is convertible to an answer to the query in the natural language. These agents communicate in an embedding space without a conversion between a natural language format and an embedding format.

Abstract: In general, the disclosure describes techniques for implementing an MI-based attack detector. In an example, a method includes training a neural network using training data, applying stochastic quantization to one or more layers of the neural network, generating, using the trained neural network, an ensemble of neural networks having a plurality of quantized members, wherein at least one of weights or activations of each of the plurality of quantized members have different bit precision, and combining predictions of the plurality of quantized members of the ensemble to detect one or more adversarial attacks and/or determine performance of the ensemble of neural networks.

Abstract: Control valves and cages that are adapted to reduce flashing and cavitation. A cage for use with a control valve having an inlet, an outlet, and defining a flow passage between the inlet and the outlet. The cage includes a generally cylindrical body and having a central bore, an upper portion, and a lower portion and an inner wall, an outer wall, and an intermediate wall disposed between the inner wall and the outer wall. The inner wall includes an inlet opening and the outer wall including an outlet opening. The inner wall, the outer wall, and the intermediate wall cooperate to define a portion of the flow passage that extends from the inlet opening, through the cage along the inner wall, along the intermediate wall, past a terminal portion of the intermediate wall, along the outer wall, to the outlet opening.

Abstract: Control valves and cages that are adapted to reduce flashing and cavitation. A cage for use with a control valve having an inlet, an outlet, and defining a flow passage between the inlet and the outlet. The cage includes a generally cylindrical body and having a central bore, an upper portion, and a lower portion and an inner wall, an outer wall, and an intermediate wall disposed between the inner wall and the outer wall. The inner wall includes an inlet opening and the outer wall including an outlet opening. The inner wall, the outer wall, and the intermediate wall cooperate to define a portion of the flow passage that extends from the inlet opening, through the cage along the inner wall, along the intermediate wall, past a terminal portion of the intermediate wall, along the outer wall, to the outlet opening.

Abstract: Systems and/or methods can include a ring based inverter chain that constructs multi-bit flip-flops that store time. The time flip-flops serve as storage units and enable pipeline operations. Single cells used in time series analysis, such as dynamic time warping are rendered by the time-domain circuits. The circuits include time flip-flops, Min, and ABS circuits. A and the matrix can be constructed through the single cells.

Abstract: Systems formed by a multi-bit three-transistor (3T) memory cell (i.e., dynamic-analog RAM) are provided. The 3T memory cell includes: a read-access transistor M1 in electrical communication with a read bitline; a switch transistor M2 in electrical communication with the read-access transistor M1 a write-access transistor M3 in electrical communication with the read-access transistor M1 and a write bitline; and a memory node MEM in electrical communication between the read-access transistor M1 and the write-access transistor M3, wherein the memory node MEM is configured to store a 4-bit weight WE. An array of the 3T memory cells (i.e., dynamic-analog RAMs) may form a computing-in-memory (CIM) macro, and further form a convolutional neural network (CNN) accelerator by communicating with an application-specific integrated circuit (ASIC) which communicates with a global weight static random access memory and an activation static random access memory.

Abstract: Systems and/or methods can include a ring based inverter chain that constructs multi-bit flip-flops that store time. The time flip-flops serve as storage units and enable pipeline operations. Single cells used in time series analysis, such as dynamic time warping are rendered by the time-domain circuits. The circuits include time flip-flops, Min, and ABS circuits. A and the matrix can be constructed through the single cells.

Abstract: Systems and methods for a low-cost mixed-signal time-domain accelerator for generative adversarial network (GAN) are provided. In one aspect, a system includes a memory and a training management unit (TMU) in communication with the memory. The TMU is configured to manage a training sequence. The system includes a time-domain multiplication-accumulation (TDMAC) unit in communication with the TMU, wherein the TDMAC unit is configured to perform time-domain multiplier operations and time-domain accumulator operations.

Abstract: Control valves and cages that are adapted to reduce flashing and cavitation. A cage for use with a control valve having an inlet, an outlet, and defining a flow passage between the inlet and the outlet. The cage includes a generally cylindrical body and having a central bore, an upper portion, and a lower portion and an inner wall, an outer wall, and an intermediate wall disposed between the inner wall and the outer wall. The inner wall includes an inlet opening and the outer wall including an outlet opening. The inner wall, the outer wall, and the intermediate wall cooperate to define a portion of the flow passage that extends from the inlet opening, through the cage along the inner wall, along the intermediate wall, past a terminal portion of the intermediate wall, along the outer wall, to the outlet opening.

Abstract: It is an object of the present disclosure to enable displaying information on unused area of an input image while displaying an enlarged image of the input image An image processing device includes a specified area setting part configured to set a specified area in an input image, an additional information setting part configured to set additional information on at least a part of non-specified area which is an area in the input image other than the specified area, and a display control part configured to display the specified area and the additional information on the display as an output image. The user can view the image of the specified area and the additional information at the same time. Therefore, the device can utilize the information of the input image more effectively.

Abstract: It is an object of the present disclosure to enable displaying information on unused area of an input image while displaying an enlarged image of the input image An image processing device includes a specified area setting part configured to set a specified area in an input image, an additional information setting part configured to set additional information on at least a part of non-specified area which is an area in the input image other than the specified area, and a display control part configured to display the specified area and the additional information on the display as an output image. The user can view the image of the specified area and the additional information at the same time. Therefore, the device can utilize the information of the input image more effectively.

Abstract: A valve plug assembly includes a support member having a support member body having a first end and a second end. A stem bore adapted to receive a valve stem may extend axially inward from the second end, and a mating protrusion may extend axially outward from the first end. The valve plug assembly also includes a plug tip having a first end and a second end, and a plug surface adapted to engage a valve seat is disposed adjacent to the first end. A mating bore may extend axially inward from the second end, and the mating protrusion may be received into the mating bore such that a threaded portion of the mating protrusion engages a threaded portion of the mating bore. Additionally, an adhesive bonds the threaded portion of the mating protrusion to the threaded portion of the mating bore.

Abstract: A valve trim apparatus comprises a valve seat (216) and a closure member (214) to operatively engage the valve seat (216). One of the closure member (214) and the valve seat (216) includes a plurality of annular ribs (222), and at least one of the valve seat (216) and the closure member (214) defines at least one groove (218) to be positioned between at least two of the annular ribs (222) to receive material from a sealing surface (220) between the closure member (214) and the valve seat (216) when the closure member (214) is sealingly engaged with the valve seat (216).

Abstract: A valve plug assembly includes a support member having a support member body having a first end and a second end. A stem bore adapted to receive a valve stem may extend axially inward from the second end, and a mating protrusion may extend axially outward from the first end. The valve plug assembly also includes a plug tip having a first end and a second end, and a plug surface adapted to engage a valve seat is disposed adjacent to the first end. A mating bore may extend axially inward from the second end, and the mating protrusion may be received into the mating bore such that a threaded portion of the mating protrusion engages a threaded portion of the mating bore. Additionally, an adhesive bonds the threaded portion of the mating protrusion to the threaded portion of the mating bore.

Abstract: A valve trim apparatus comprises a valve seat (216) and a closure member (214) to operatively engage the valve seat (216). One of the closure member (214) and the valve seat (216) includes a plurality of annular ribs (222), and at least one of the valve seat (216) and the closure member (214) defines at least one groove (218) to be positioned between at least two of the annular ribs (222) to receive material from a sealing surface (220) between the closure member (214) and the valve seat (216) when the closure member (214) is sealingly engaged with the valve seat (216).

Abstract: A method and apparatus for stabilizing the output of a mode-locked laser by monitoring the temporal behavior of the pulse train profile and controlling the laser cavity optical length and/or loss modulation frequency accordingly. A mismatch of the cavity optical length and the loss modulation frequency will yield a first characteristic noise condition on the laser beam pulse train when the optical length is too short for a given loss modulation frequency and a second, different noise condition when the optical length is too long. The laser beam is monitored and analyzed to determine which noise condition is present. The cavity optical length is adjusted accordingly by movement of one or more optical elements or by changing the index of refraction of one or more optical elements. In the alternative, or additionally, the loss modulation frequency can be adjusted to bring the laser back into mode lock.