Abstract: An integrated circuit, in accordance with embodiments of the present technology, includes a plurality of engines, a plurality of engine level power gating (ELPG) controllers, and a power gating arbiter for implementing engine level power gating arbitration techniques. The power gating arbiter may receive requests from one or more ELPG controllers to turn on their respective engines or portions therein. The power gating arbiter prioritizes the request and sends an acknowledgment to a given ELPG controller to turn on or off its corresponding engine according to the prioritized predetermined order. After receiving the acknowledgement, the given ELPG controller turns on or off its corresponding engine and returns an indication to the power gating arbiter that the corresponding engine is turned on or off. The process may be iteratively repeated for each received request after receiving the indication from the previously serviced ELPG controller that its corresponding engine is turned on or off.

Abstract: An integrated circuit, in accordance with embodiments of the present technology, includes a plurality of engines, a plurality of engine level power gating (ELPG) controllers, and a power gating arbiter for implementing engine level power gating arbitration techniques. The power gating arbiter may receive requests from one or more ELPG controllers to turn on their respective engines or portions therein. The power gating arbiter prioritizes the request and sends an acknowledgment to a given ELPG controller to turn on or off its corresponding engine according to the prioritized predetermined order. After receiving the acknowledgement, the given ELPG controller turns on or off its corresponding engine and returns an indication to the power gating arbiter that the corresponding engine is turned on or off. The process may be iteratively repeated for each received request after receiving the indication from the previously serviced ELPG controller that its corresponding engine is turned on or off.

Abstract: The present invention provides a unified inverse discrete cosine transform (IDCT) microcode processor engine, which is able to process IDCT with different video standards and also achieves the processing speed requirement. The microcode processor engine comprises a read unit for reading input data; a shift left unit comprising: a first shift left block for left-shifting input data; and a second shift left block for left-shifting input data; an add unit for adding data output from the shift left unit; and a shift right unit for right-shifting data output from the add unit. The present invention also provides a system of inverse discrete cosine transform.

Abstract: The present invention provides a unified inverse discrete cosine transform (IDCT) microcode processor engine, which is able to process IDCT with different video standards and also achieves the processing speed requirement. The microcode processor engine comprises a read unit for reading input data; a shift left unit comprising: a first shift left block for left-shifting input data; and a second shift left block for left-shifting input data; an add unit for adding data output from the shift left unit; and a shift right unit for right-shifting data output from the add unit. The present invention also provides a system of inverse discrete cosine transform.