Abstract: A display panel is provided, including a flat display region, and a fixed region and a sliding-scrolling region on two sides of the flat display region in a first direction, the fixed region is adhered with a middle frame, the flat display region is configured to display images, the sliding-scrolling region is configured to form a rolled-up state and an extended state by sliding-scrolling, the sliding-scrolling region displays the image together with the flat display region in the extended state, on a plane perpendicular to the display panel, the display panel at least includes a display substrate, an adhesive layer disposed on the display substrate, and a cover plate layer on a side of the adhesive layer away from the display substrate, the cover plate layer at least includes a glass layer, the glass layer of at least one of the fixed region and the sliding-scrolling region has a structural hole.

Abstract: Embodiments described herein relate to a system and method for providing flexible receiver configuration in wireless communication systems, such as 802.11 WLAN systems. In one embodiment, a wireless device may transmit a first data frame including first configuration information specifying a first configuration of the receiver to notify a remote device that the wireless device intends to configure its receiver according to the first configuration. After receiving an acknowledgement frame confirming the first configuration information, the wireless device may configure the receiver according to the first configuration. In another embodiment, a wireless device may receive a first data frame including first configuration information and further including a request that the wireless device configure its receiver according to the first configuration. In response, the wireless device may configure the receiver according to the first configuration.

Abstract: A semiconductor package structure having a frontside redistribution layer, a stacking structure disposed over the frontside redistribution layer and having a first semiconductor die and a second semiconductor die over the first semiconductor die. A backside redistribution layer is disposed over the stacking structure, a first intellectual property (IP) core is disposed in the stacking structure and electrically coupled to the frontside redistribution layer through a first routing channel. A second IP core is disposed in the stacking structure and is electrically coupled to the backside redistribution layer through a second routing channel, wherein the second routing channel is different from the first routing channel and electrically insulated from the frontside redistribution layer.

Abstract: A device, a method for determining relative positions of power consumers based on a high-frequency signal, and a computer-readable storage medium are provided. The device is applied to a distribution transformer supply zone. The device includes a resonance or signal generator and a direction detector, the resonance or signal generator is disposed in a user electricity meter, the direction detector is disposed on a power line, the resonance or signal generator is configured to transmit a high-frequency signal or generate resonance in response to the high-frequency signal; the direction detector is configured to monitor a voltage and a current of the high-frequency signal flowing into the user electricity meter, and determine, based on a phase difference between the voltage and the current, a relative position relationship of two adjacent user electricity meters on the power line.

Abstract: The present invention provides a semiconductor structure, wherein the semiconductor structure includes an oxide definition region, a plurality of metal gate structures and a plurality of S/D contacts. The oxide definition region is disposed over a semiconductor substrate and surrounded by insulating regions. The plurality of metal gate structures are disposed on an N-well or a P-well manufactured on the semiconductor substrate. The plurality of S/D contacts are disposed on the N-well or the P-well manufactured on the semiconductor substrate. In addition, the plurality of metal gate structures, the plurality of S/D contacts and the at least one dummy gate structure are within the oxide definition region.

Abstract: A semiconductor package includes a first die comprising an upper surface and a lower surface opposite to the upper surface. The first die includes a plurality of through-silicon vias (TSVs) penetrating through the first die. A second die is stacked on the upper surface of the first die. An interposer layer is disposed on the lower surface of the first die. An inductor is disposed in the interposer layer. The inductor comprises terminals directly coupled to the TSVs.

Abstract: Embodiments described herein relate to a system and method for providing flexible receiver configuration in wireless communication systems, such as 802.11 WLAN systems. In one embodiment, a wireless device may transmit a first data frame including first configuration information specifying a first configuration of the receiver to notify a remote device that the wireless device intends to configure its receiver according to the first configuration. After receiving an acknowledgement frame confirming the first configuration information, the wireless device may configure the receiver according to the first configuration. In another embodiment, a wireless device may receive a first data frame including first configuration information and further including a request that the wireless device configure its receiver according to the first configuration. In response, the wireless device may configure the receiver according to the first configuration.

Abstract: A semiconductor structure is provided. The semiconductor structure includes a semiconductor substrate, first and second well regions, first and second gate-all-around (GAA) field-effect transistor devices and a first dielectric layer. The first and second well regions are arranged in the semiconductor substrate and separated from each other. Top and bottom surfaces of the first and second well regions are aligned with top and bottom surfaces of the semiconductor substrate. The first and second GAA field-effect transistor devices are formed over the first and second well regions. A first gate structure of the first GAA field-effect transistor device is electrically connected to a power supply terminal. The first epitaxial source/drain features of the first GAA field-effect transistor are electrically connected to the second gate structure of the second GAA field-effect transistor.

Abstract: Under dynamic shard mapping, applications may dynamically define, evolve, and redefine how a sharded table is sharded across shards according to sharding keys. Dynamic shard mapping is referred to as being dynamic because changes to a sharding directory that defines a sharding distribution scheme are effected without having to change synchronized f metadata. A sharding directory maps sharding key values to shard servers. The changes are effected directly by invoking an API or indirectly by submitting a DML command that includes, for example, a sharding key value that is unmapped by the sharding directory. The sharding directory is distributed among the shards and client computers of a sharded DBMS to facilitate and optimize the routing of database commands across the shards of a DBMS.

Abstract: The present disclosure discloses a card holder, which includes a shell and an elastic piece. The shell having a first accommodating cavity and a first accommodating opening, the first accommodating opening being communicated with the first accommodating cavity, and first accommodating cavity being used for accommodating a card. The elastic piece being arranged in the first accommodating cavity, and the elastic piece being used for pressing and locking the card in the first accommodating cavity. Through the structure, when the card is placed in the first accommodating cavity through the first accommodating opening. The elastic piece arranged in the first accommodating cavity is pressed by both sides of the card. An elastic reset force generated when the elastic piece is pressed tightly presses the card in the first accommodating cavity, which can effectively prevent the card from sliding out of the first accommodating cavity through the first accommodating opening.

Abstract: Semiconductor structures of Schottky devices are provided. An N-type well region and a P-type well region are formed over a P-type semiconductor substrate. A first active region is formed over the P-type well region, and includes a plurality of first fins. A second active region is formed over the N-type well region, and includes a plurality of second fins. A third active region is formed over the N-type well region, and includes a plurality of third fins. A plurality of electrodes are formed over the third active region. The electrodes, the first source/drain features and the second source/drain features are formed in the same level. An emitter region of a Schottky BJT is formed by the electrodes, a base region of the Schottky BJT is formed by the N-type well region, and a collector region of the Schottky BJT is formed by the P-type semiconductor substrate.

Abstract: The present disclosure provides a card holder wallet. The card holder wallet includes: a shell and a flexible protective sleeve. The shell is provided with a first accommodating cavity and a first accommodating opening. The first accommodating opening is communicated with the first accommodating cavity. The first accommodating cavity is configured to accommodate a card. The protective sleeve is provided with a first portion and a second portion. The second portion and the first portion are rotatable. The first portion is connected to the shell. The second portion can rotate to cover the first accommodating opening. The protective sleeve is provided with a seventh accommodating cavity and a seventh accommodating opening. The seventh accommodating opening is communicated with the seventh accommodating cavity, and the seventh accommodating cavity is configured to accommodate money.

Abstract: Bipolar junction transistor (BJT) structures are provided. First and second well regions are formed over a dielectric layer. A plurality of first and second gate-all-around (GAA) field-effect transistors are formed over a first well region. A plurality of third GAA field-effect transistors are formed over the second well region. Source/drain features of the first and third GAA field-effect transistors and the second well region have a first conductivity type. Source/drain features of the second GAA field-effect transistors and the first well region have a second conductivity type that is different from the first conductivity type. A first PN junction of a first BJT device is formed between the source/drain features of the first GAA field-effect transistors and the first well region, and a second PN junction of the first BJT device is formed between the first well region and the second well region.

Abstract: A semiconductor package includes a first die comprising an upper surface and a lower surface opposite to the upper surface. The first die includes a plurality of through-silicon vias (TSVs) penetrating through the first die. A second die is stacked on the upper surface of the first die. An interposer layer is disposed on the lower surface of the first die. An inductor is disposed in the interposer layer. The inductor comprises terminals directly coupled to the TSVs.

Abstract: In one aspect, separator-free energy storage devices are disclosed. Such devices comprise a first electrode and a second electrode. In some embodiments, the first electrode is opposite the second electrode. The first and/or second electrodes are formed from a nanocomposite material. The nanocomposite material includes plurality of carbon nanostructures, each of which is at least partially coated with a layer of material comprising a transition metal oxide. In some embodiments, the coating layer is uniform or substantially uniform in one or more properties.

Abstract: A semiconductor structure is provided. The semiconductor structure includes a logic cell. The logic cell includes a first transistor and a second transistor. The first transistor includes a first gate structure extending in a first direction and overlapping a first semiconductor fin. The second transistor includes a second gate structure extending in the first direction and overlapping the first semiconductor fin and a second semiconductor fin. The first and second semiconductor fins extend in a second direction that is perpendicular to the first direction. The first and second transistors share a source/drain region, and one end of the first gate structure is formed between the first and second semiconductor fins.

Abstract: The present disclosure relates to the technical field of rapid detection of molecules, and specifically relates to a method for rapid fluorescent immunoassay (FIA) and chemiluminescent immunoassay (CLIA) based on electrokinetic acceleration. The method includes the following steps sequentially: S1. sample acceleration: applying an actuating signal to a chip on which a target molecule is dripped to obtain a chip binding to the target molecule, where the chip includes an electrode sheet and coating molecules is immobilized on the electrode sheet; and S2. secondary antibody acceleration: adding a secondary antibody for binding to the target molecule dropwise on the chip binding to the target molecule, and applying an actuating signal to the chip to obtain a chip binding to the secondary antibody. The method can effectively improve a rate of FIA and CLIA, and can speed up a detection process and meet the need for rapid point-of-care testing (POCT).

Abstract: Embodiments described herein relate to a system and method for providing flexible receiver configuration in wireless communication systems, such as 802.11 WLAN systems. In one embodiment, a wireless device may transmit a first data frame including first configuration information specifying a first configuration of the receiver to notify a remote device that the wireless device intends to configure its receiver according to the first configuration. After receiving an acknowledgement frame confirming the first configuration information, the wireless device may configure the receiver according to the first configuration. In another embodiment, a wireless device may receive a first data frame including first configuration information and further including a request that the wireless device configure its receiver according to the first configuration. In response, the wireless device may configure the receiver according to the first configuration.

Abstract: Semiconductor structures of bipolar junction transistor (BJT) are provided. A first active region of a collection region is formed over a first P-type well region. Second and third active regions of a base region are formed over an N-type well region. A fourth active region of an emitter region is formed over a second P-type well region. The first active region includes a plurality of first fins and a plurality of first source/drain features epitaxially grown on the first fins. Each of the second and third active regions includes a plurality of second fins and a plurality of second source/drain features epitaxially grown on the second fins. The fourth active region includes a plurality of third fins and a plurality of third source/drain features epitaxially grown on the third fins. The second and third active regions are disposed on opposite sides of the fourth active region.