Patents by Inventor Zheng Zeng
Zheng Zeng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11969066Abstract: The present disclosure provides a card holder wallet. The card holder wallet includes: a shell and a flexible protective sleeve. The shell is provided with a first accommodating cavity and a first accommodating opening. The first accommodating opening is communicated with the first accommodating cavity. The first accommodating cavity is configured to accommodate a card. The protective sleeve is provided with a first portion and a second portion. The second portion and the first portion are rotatable. The first portion is connected to the shell. The second portion can rotate to cover the first accommodating opening. The protective sleeve is provided with a seventh accommodating cavity and a seventh accommodating opening. The seventh accommodating opening is communicated with the seventh accommodating cavity, and the seventh accommodating cavity is configured to accommodate money.Type: GrantFiled: October 12, 2023Date of Patent: April 30, 2024Inventor: Zheng Zeng
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Publication number: 20240128262Abstract: Bipolar junction transistor (BJT) structures are provided. First and second well regions are formed over a dielectric layer. A plurality of first and second gate-all-around (GAA) field-effect transistors are formed over a first well region. A plurality of third GAA field-effect transistors are formed over the second well region. Source/drain features of the first and third GAA field-effect transistors and the second well region have a first conductivity type. Source/drain features of the second GAA field-effect transistors and the first well region have a second conductivity type that is different from the first conductivity type. A first PN junction of a first BJT device is formed between the source/drain features of the first GAA field-effect transistors and the first well region, and a second PN junction of the first BJT device is formed between the first well region and the second well region.Type: ApplicationFiled: September 5, 2023Publication date: April 18, 2024Inventors: Shih-Chuan CHIU, Chia-Hsin HU, Zheng ZENG
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Publication number: 20240079444Abstract: A semiconductor package includes a first die comprising an upper surface and a lower surface opposite to the upper surface. The first die includes a plurality of through-silicon vias (TSVs) penetrating through the first die. A second die is stacked on the upper surface of the first die. An interposer layer is disposed on the lower surface of the first die. An inductor is disposed in the interposer layer. The inductor comprises terminals directly coupled to the TSVs.Type: ApplicationFiled: June 12, 2023Publication date: March 7, 2024Applicant: MediaTek Inc.Inventors: Zheng Zeng, Ching-Chung Ko, Kuei-Ti Chan
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Patent number: 11915871Abstract: In one aspect, separator-free energy storage devices are disclosed. Such devices comprise a first electrode and a second electrode. In some embodiments, the first electrode is opposite the second electrode. The first and/or second electrodes are formed from a nanocomposite material. The nanocomposite material includes plurality of carbon nanostructures, each of which is at least partially coated with a layer of material comprising a transition metal oxide. In some embodiments, the coating layer is uniform or substantially uniform in one or more properties.Type: GrantFiled: March 29, 2018Date of Patent: February 27, 2024Assignee: THE UNIVERSITY OF NORTH CAROLINA AT GREENSBOROInventors: Jianjun Wei, Yiyang Liu, Zheng Zeng
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Publication number: 20240038755Abstract: A semiconductor structure is provided. The semiconductor structure includes a logic cell. The logic cell includes a first transistor and a second transistor. The first transistor includes a first gate structure extending in a first direction and overlapping a first semiconductor fin. The second transistor includes a second gate structure extending in the first direction and overlapping the first semiconductor fin and a second semiconductor fin. The first and second semiconductor fins extend in a second direction that is perpendicular to the first direction. The first and second transistors share a source/drain region, and one end of the first gate structure is formed between the first and second semiconductor fins.Type: ApplicationFiled: June 29, 2023Publication date: February 1, 2024Inventors: Chia-Hsin HU, Wei-Chieh TSENG, Zheng ZENG
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Patent number: 11877348Abstract: Embodiments described herein relate to a system and method for providing flexible receiver configuration in wireless communication systems, such as 802.11 WLAN systems. In one embodiment, a wireless device may transmit a first data frame including first configuration information specifying a first configuration of the receiver to notify a remote device that the wireless device intends to configure its receiver according to the first configuration. After receiving an acknowledgement frame confirming the first configuration information, the wireless device may configure the receiver according to the first configuration. In another embodiment, a wireless device may receive a first data frame including first configuration information and further including a request that the wireless device configure its receiver according to the first configuration. In response, the wireless device may configure the receiver according to the first configuration.Type: GrantFiled: January 7, 2022Date of Patent: January 16, 2024Assignee: Apple Inc.Inventors: Chiu Ngok E. Wong, Christiaan A. Hartman, Zheng Zeng, Joonsuk Kim, Su Khiong Yong, Yong Liu
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Patent number: 11874275Abstract: The present disclosure relates to the technical field of rapid detection of molecules, and specifically relates to a method for rapid fluorescent immunoassay (FIA) and chemiluminescent immunoassay (CLIA) based on electrokinetic acceleration. The method includes the following steps sequentially: S1. sample acceleration: applying an actuating signal to a chip on which a target molecule is dripped to obtain a chip binding to the target molecule, where the chip includes an electrode sheet and coating molecules is immobilized on the electrode sheet; and S2. secondary antibody acceleration: adding a secondary antibody for binding to the target molecule dropwise on the chip binding to the target molecule, and applying an actuating signal to the chip to obtain a chip binding to the secondary antibody. The method can effectively improve a rate of FIA and CLIA, and can speed up a detection process and meet the need for rapid point-of-care testing (POCT).Type: GrantFiled: June 5, 2023Date of Patent: January 16, 2024Assignee: FOSHAN MICROWONDERS BIOTECHNOLOGY CO., LTD.Inventors: Xiaozhu Liu, Hai Xu, Yanmin Li, Jun Li, Yong Hu, Li Tong, Jie Lin, Zhidong Zhang, Lihua Yang, Liang Ma, Zheng Zeng, Linggao Zeng, Li Chen, Shengxi Wu, Shenghui Qin
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Publication number: 20240014295Abstract: Semiconductor structures of bipolar junction transistor (BJT) are provided. A first active region of a collection region is formed over a first P-type well region. Second and third active regions of a base region are formed over an N-type well region. A fourth active region of an emitter region is formed over a second P-type well region. The first active region includes a plurality of first fins and a plurality of first source/drain features epitaxially grown on the first fins. Each of the second and third active regions includes a plurality of second fins and a plurality of second source/drain features epitaxially grown on the second fins. The fourth active region includes a plurality of third fins and a plurality of third source/drain features epitaxially grown on the third fins. The second and third active regions are disposed on opposite sides of the fourth active region.Type: ApplicationFiled: June 1, 2023Publication date: January 11, 2024Inventors: Shih-Chuan CHIU, Chia-Hsin HU, Zheng ZENG
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Publication number: 20230387716Abstract: A device, a method for determining relative positions of power consumers based on a high-frequency signal, and a computer-readable storage medium are provided. The device is applied to a distribution transformer supply zone. The device includes a resonance or signal generator and a direction detector, the resonance or signal generator is disposed in a user electricity meter, the direction detector is disposed on a power line, the resonance or signal generator is configured to transmit a high-frequency signal or generate resonance in response to the high-frequency signal; the direction detector is configured to monitor a voltage and a current of the high-frequency signal flowing into the user electricity meter, and determine, based on a phase difference between the voltage and the current, a relative position relationship of two adjacent user electricity meters on the power line.Type: ApplicationFiled: December 7, 2021Publication date: November 30, 2023Applicant: CHINA SOUTHERN POWER GRID TECHNOLOGY CO., LTD.Inventors: Sijian ZHANG, Xiaoping ZHANG, Guan CHEN, Zheng ZENG, Zihang HUO, Jiaming WU
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Publication number: 20230328935Abstract: This disclosure provides a design method for a radiator of a vehicle power module. The design method includes: selecting a plurality of specific values from the possible value ranges of the first distance D1, the second distance D2 and the radius R, respectively, to form different combinations of the plurality of specific values, performing simulation calculations on the different combinations, and obtaining a temperature rise ?Tj and a pressure drop ?Pf corresponding to each combination to form a plurality of samples; through a response surface method, fitting explicit functions of the temperature rise ?Tj and the pressure drop ?Pf with the first distance D1, the second distance D2 and the radius R as dependent variables; and through a multi-objective optimization, determining the first distance D1, the second distance D2 and the radius R with an optimization objective that the temperature rise ?Tj and the pressure drop ?Pf are simultaneously minimized.Type: ApplicationFiled: April 6, 2023Publication date: October 12, 2023Applicants: Nexperia Technology (Shanghai) Ltd., Chongqing University, NEXPERIA B.V.Inventors: Ke Jiang, Zheng Zeng, Chunlin Zhu, Jiawei Zhang, Richard Qian, Peng Sun, Minhui Ma, Yuxi Liang
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Publication number: 20230324380Abstract: The present disclosure relates to the technical field of rapid detection of molecules, and specifically relates to a method for rapid fluorescent immunoassay (FIA) and chemiluminescent immunoassay (CLIA) based on electrokinetic acceleration. The method includes the following steps sequentially: S1. sample acceleration: applying an actuating signal to a chip on which a target molecule is dripped to obtain a chip binding to the target molecule, where the chip includes an electrode sheet and coating molecules is immobilized on the electrode sheet; and S2. secondary antibody acceleration: adding a secondary antibody for binding to the target molecule dropwise on the chip binding to the target molecule, and applying an actuating signal to the chip to obtain a chip binding to the secondary antibody. The method can effectively improve a rate of FIA and CLIA, and can speed up a detection process and meet the need for rapid point-of-care testing (POCT).Type: ApplicationFiled: June 5, 2023Publication date: October 12, 2023Inventors: Xiaozhu Liu, Hai Xu, Yanmin Li, Jun Li, Yong Hu, Li Tong, Jie Lin, Zhidong Zhang, Lihua Yang, Liang Ma, Zheng Zeng, Linggao Zeng, Li Chen, Shengxi Wu, Shenghui Qin
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Publication number: 20230317580Abstract: A semiconductor package structure having a frontside redistribution layer, a stacking structure disposed over the frontside redistribution layer and having a first semiconductor die and a second semiconductor die over the first semiconductor die. A backside redistribution layer is disposed over the stacking structure, a first intellectual property (IP) core is disposed in the stacking structure and electrically coupled to the frontside redistribution layer through a first routing channel. A second IP core is disposed in the stacking structure and is electrically coupled to the backside redistribution layer through a second routing channel, wherein the second routing channel is different from the first routing channel and electrically insulated from the frontside redistribution layer.Type: ApplicationFiled: June 6, 2023Publication date: October 5, 2023Inventors: Hsing-Chih LIU, Zheng ZENG, Che-Hung KUO
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Patent number: 11715754Abstract: A semiconductor package includes a first die comprising an upper surface and a lower surface opposite to the upper surface. The first die includes a plurality of through-silicon vias (TSVs) penetrating through the first die. A second die is stacked on the upper surface of the first die. An interposer layer is disposed on the lower surface of the first die. An inductor is disposed in the interposer layer. The inductor comprises terminals directly coupled to the TSVs.Type: GrantFiled: May 12, 2021Date of Patent: August 1, 2023Assignee: MediaTek Inc.Inventors: Zheng Zeng, Ching-Chung Ko, Kuei-Ti Chan
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Patent number: 11710688Abstract: A semiconductor package structure includes a frontside redistribution layer, a stacking structure, a backside redistribution layer, a first intellectual property (IP) core, and a second IP core. The stacking structure is disposed over the frontside redistribution layer and comprises a first semiconductor die and a second semiconductor die over the first semiconductor die. The backside redistribution layer is disposed over the stacking structure. The first IP core is disposed in the stacking structure and is electrically coupled to the frontside redistribution layer through a first routing channel. The second IP core is disposed in the stacking structure and is electrically coupled to the backside redistribution layer through a second routing channel, wherein the second routing channel is separated from the first routing channel and electrically insulated from the frontside redistribution layer.Type: GrantFiled: June 30, 2021Date of Patent: July 25, 2023Assignee: MEDIATEK INC.Inventors: Hsing-Chih Liu, Zheng Zeng, Che-Hung Kuo
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Patent number: 11530036Abstract: A fixed-wing aerial underwater vehicle includes a shell component, a flight component and a pneumatic buoyancy component. The flight component includes a fixed wing and rotors, and the fixed wing and the rotors are mounted in the shell component. The pneumatic buoyancy component includes an air bladder and an inflation and deflation portion, and the inflation and deflation portion can inflate and deflate the air bladder. The air bladder is installed on the shell component, a containing space is formed in the shell component, and the inflation and deflation portion is partially or entirely installed in the containing space. Each rotor includes a rotor supporting rod, a motor base, a motor and a propeller, which are sequentially connected. A control method for the fixed-wing aerial underwater vehicle mentioned above is further provided.Type: GrantFiled: January 10, 2018Date of Patent: December 20, 2022Assignee: SHANGHAI JIAO TONG UNIVERSITYInventors: Zheng Zeng, Lian Lian, Di Lu, Ping Ren, Xiafei Ma
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Publication number: 20220262578Abstract: In one aspect, separator-free energy storage devices are disclosed. Such devices comprise a first electrode and a second electrode. In some embodiments, the first electrode is opposite the second electrode. The first and/or second electrodes are formed from a nanocomposite material. The nanocomposite material includes plurality of carbon nanostructures, each of which is at least partially coated with a layer of material comprising a transition metal oxide. In some embodiments, the coating layer is uniform or substantially uniform in one or more properties.Type: ApplicationFiled: March 29, 2018Publication date: August 18, 2022Inventors: Jianjun WEI, Yiyang LIU, Zheng ZENG
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Patent number: 11367788Abstract: A semiconductor device structure is provided. A first well region with a first type of conductivity is formed over a semiconductor substrate. A second well region with a second type of conductivity is formed over the semiconductor substrate. A well region is formed over the semiconductor substrate and between the first and second well regions. A first gate structure is disposed on the well region and partially over the first and second well regions. A drain region is in the first well region. A source region and a bulk region are in the second well region. The drain region, the source region and the bulk region have the first type of conductivity. A second gate structure is disposed on the second well region, and separated from the first gate structure by the source region and the bulk region.Type: GrantFiled: April 21, 2020Date of Patent: June 21, 2022Assignee: MEDIATEK INC.Inventors: Jing-Chyi Liao, Ching-Chung Ko, Zheng Zeng
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Patent number: D977831Type: GrantFiled: January 17, 2022Date of Patent: February 14, 2023Inventor: Zheng Zeng
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Patent number: D1003037Type: GrantFiled: June 15, 2023Date of Patent: October 31, 2023Assignee: Shenzhen Wanhui Technology Innovation Co., Ltd.Inventor: Zheng Zeng
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Patent number: D1009465Type: GrantFiled: July 13, 2023Date of Patent: January 2, 2024Assignee: Shenzhen Wanhui Technology Innovation Co., Ltd.Inventor: Zheng Zeng