Abstract: Disclosed are a SOC-based task scheduling method, a SOC, and an electronic device. The task scheduling method includes: determining a task set to be executed by the SOC and dependency relationships between respective tasks in the task set; determining, based on the task set and the dependency relationships, first scheduling information for a first task executable by a first accelerator in the SOC; transmitting, by a first task scheduler in the SOC, the first scheduling information to a second task scheduler, in the SOC, that is configured to schedule the first accelerator; and scheduling the first accelerator by the second task scheduler based on the first scheduling information, and executing the first task by the first accelerator.

Abstract: A display module includes a display panel having a fingerprint identification area and a light-transmitting protective film located on a back surface of the display panel. The light-transmitting protective film includes a protective layer, a light-shielding pattern located on a side of the protective layer, and a light-transmitting adhesive layer located on a side of the light-shielding pattern away from the protective layer. The protective layer has a target area. At least the target area is a light-transmitting area, and the target area at least partially overlaps with the fingerprint identification area. The light-shielding pattern defines a plurality of imaging apertures, the plurality of imaging apertures are arranged at intervals, and orthogonal projection of the plurality of imaging apertures on the protective layer are at least located in the target area. A surface of the light-transmitting adhesive layer away from the light-shielding pattern is in contact with the display panel.

Abstract: A method for manufacturing a merged PiN Schottky (MPS) diode may include steps of providing a substrate having a first conductivity type; forming an epitaxial layer with the first conductivity type on top of the substrate; forming a plurality of regions with a second conductivity type under a top surface of the epitaxial layer; forming a plasma spreading layer; depositing and patterning a first Ohmic contact metal on the regions with the second conductivity type; depositing a Schottky contact metal on top of the entire epitaxial layer; and forming a second Ohmic contact metal on a backside of the substrate. In another embodiment, the step of forming a plurality of regions with a second conductivity type may include steps of depositing and patterning a mask layer on the epitaxial layer, implanting P-type dopant into the epitaxial layer, and removing the mask layer.

Abstract: A display panel and a display device are provided. The display panel comprises a substrate, a plurality of sub-pixels, a plurality of data lines, a plurality of wiring structures and a plurality of pads. The substrate comprises a display area and a non-display area comprising a bending area. The sub-pixels and data lines are in the display area and electrically connected with each other. The wiring structures are in the bending area and electrically connected with the data lines. At least one wiring structure comprises a plurality of hollow patterns connected successively, each hollow pattern comprises a first conductive part and a second conductive part connected with each other. The plurality of pads are in the non-display area and located on a side of the plurality of wiring structures away from the display area and electrically connected with the plurality of wiring structures.

Abstract: A method for manufacturing a merged PiN Schottky (MPS) diode may include steps of providing a substrate having a first conductivity type; forming an epitaxial layer with the first conductivity type on top of the substrate; forming a plurality of regions with a second conductivity type under a top surface of the epitaxial layer; forming a plasma spreading layer; depositing and patterning a first Ohmic contact metal on the regions with the second conductivity type; depositing a Schottky contact metal on top of the entire epitaxial layer; and forming a second Ohmic contact metal on a backside of the substrate. In another embodiment, the step of forming a plurality of regions with a second conductivity type may include steps of depositing and patterning a mask layer on the epitaxial layer, implanting P-type dopant into the epitaxial layer, and removing the mask layer.

Abstract: A method for manufacturing a merged PiN Schottky (MPS) diode may include steps of providing a substrate having a first conductivity type; forming an epitaxial layer with the first conductivity type on top of the substrate; forming a plurality of regions with a second conductivity type under a top surface of the epitaxial layer; forming a plasma spreading layer; depositing and patterning a first Ohmic contact metal on the regions with the second conductivity type; depositing a Schottky contact metal on top of the entire epitaxial layer; and forming a second Ohmic contact metal on a backside of the substrate. In another embodiment, the step of forming a plurality of regions with a second conductivity type may include steps of depositing and patterning a mask layer on the epitaxial layer, implanting P-type dopant into the epitaxial layer, and removing the mask layer.

Abstract: In one aspect, a semiconductor device may include a semiconductor substrate formed of silicon carbide; and an edge termination having a first metal layer and a second metal layer, wherein the first metal layer is deposited and patterned spacedly on the semiconductor substrate and the second metal layer is deposited and patterned onto at least a portion of the spaced first metal layer and onto the semiconductor substrate between said spaced first metal layer, and wherein the first metal layer comprises a high work function metal, while the second metal layer comprises a low work function metal. In one embodiment, the high work function metal includes Silver, Aluminum, Chromium, Nickel, and Gold; and the low work function metal includes Titanium and Nickel Silicide.

Abstract: A semiconductor device comprising a substrate having a first conductivity type; an epitaxial layer having the first conductivity type deposited on the substrate; and a MOS structure formed on the epitaxial layer; said MOS structure including multiple well regions with a second conductivity type; multiple source regions with highly doped first conductivity type formed in the well regions; multiple highly doped regions of the second conductivity type formed in the well regions; an insulating gate oxide layer formed on top of the epitaxial layer and spanned adjacent wells and source regions; and a gate electrode formed above the gate oxide layer and spanned adjacent wells and source regions, wherein a JFET region is formed between two adjacent wells; and one or more central implant regions are added with the second conductivity type on a surface of the JFET region to reduce an electric field in the gate oxide.

Abstract: A method for manufacturing a merged PiN Schottky (MPS) diode may include steps of providing a substrate having a first conductivity type; forming an epitaxial layer with the first conductivity type on top of the substrate; forming a plurality of regions with a second conductivity type under a top surface of the epitaxial layer; forming a plasma spreading layer; depositing and patterning a first Ohmic contact metal on the regions with the second conductivity type; depositing a Schottky contact metal on top of the entire epitaxial layer; and forming a second Ohmic contact metal on a backside of the substrate. In another embodiment, the step of forming a plurality of regions with a second conductivity type may include steps of depositing and patterning a mask layer on the epitaxial layer, implanting P-type dopant into the epitaxial layer, and removing the mask layer.

Abstract: A method for manufacturing a merged PiN Schottky (MPS) diode may include steps of providing a substrate having a first conductivity type; forming an epitaxial layer with the first conductivity type on top of the substrate; forming a plurality of regions with a second conductivity type under a top surface of the epitaxial layer; forming a plasma spreading layer; depositing and patterning a first Ohmic contact metal on the regions with the second conductivity type; depositing a Schottky contact metal on top of the entire epitaxial layer; and forming a second Ohmic contact metal on a backside of the substrate. In another embodiment, the step of forming a plurality of regions with a second conductivity type may include steps of depositing and patterning a mask layer on the epitaxial layer, implanting P-type dopant into the epitaxial layer, and removing the mask layer.

Abstract: A semiconductor device may include a substrate having a first conductivity type; an epitaxial layer having the first conductivity type deposited on one side of the substrate; a plurality of regions having a second conductivity type formed under a top surface of the epitaxial layer; a first Ohmic metal patterned and deposited on top of the regions with the second conductivity type; a Schottky contact metal deposited on top of the entire epitaxial layer to form a Schottky junction; and a second Ohmic metal deposited on a backside of the substrate, wherein the regions include one or more wide regions, each having different widths that can be optimized to simultaneously obtain high surge current capability and preserve a low forward voltage drop and reverse leakage current.

Abstract: In one aspect, a power converter may include a plurality of inductor banks; a plurality of switches, each switch has a first power node and a second power node, and one control node that receives a control signal that maintains the switch in either ON state in which the circuit path between the first node and the second node are established, or OFF state in which the circuit path between the first node and the second node are eliminated; and a control logic that generates multiple signals that are applied to the control nodes of the switches. In one embodiment, the switches are MOSFETs; the first power nodes are drains and the second power nodes are sources, and the control nodes are gates.

Abstract: A power converter may include a plurality of inductor banks; a plurality of capacitor banks; an intermediate bus capacitor bank; a plurality of switches, each switch has a first power node, a second power node and one control nodes that receives a control signal that maintains the switch in either ON state in which the circuit path between the first power node and the second power node are established, or OFF state in which the circuit path between the first power node and the second power node are eliminated, and a control logic that generates a plurality of signal combinations that are applied to the control nodes of said plurality of switches to enable the power converter to have a smooth voltage output and enhanced tolerance for a low voltage input bus for all signal combinations.

Abstract: A power converter may include a plurality of inductor banks; a plurality of capacitor banks; a plurality of switches, each switch having two power nodes and one control node that receives a control signal that maintains the switch in either ON state in which the circuit path between the first node and the second node are established, or OFF state in which the circuit path between the first node and the second node are eliminated; and a control logic that generates multiple signal combinations that are applied to the control nodes of the switches so that for each signal combination the power converter is configured to generate different voltage outputs. In one embodiment, the control logic generates control signals to cause zero current switching on each switch.

Abstract: In one aspect, a power converter may include a plurality of inductor banks; a plurality of capacitor banks; an intermediate bus capacitor bank; a plurality of switches, each switch has a first power node and a second power node, and one control node that receives a control signal that maintains the switch in either ON state in which the circuit path between the first node and the second node are established, or OFF state in which the circuit path between the first node and the second node are eliminated; and a control logic that generates a plurality of signal combinations that are applied to the control nodes of said plurality of switches to enable the power converter to have a smooth voltage output and enhanced tolerance for a low voltage input bus for all signal combinations.

Abstract: A method for manufacturing a Silicon Carbide (SiC) Schottky diode may include steps of providing a substrate; forming a first epitaxial layer with a first conductivity type on top of the substrate; forming a second epitaxial layer with a second conductivity type on top of the first epitaxial layer; forming a third epitaxial layer with the second conductivity type on top of the second epitaxial layer; patterning and etching the second and third epitaxial layers to form a plurality of trenches; depositing a first ohmic contact metal on a backside of the substrate; forming a second ohmic contact metal on top of the second epitaxial layer; forming a Schottky contact metal at a bottom portion of each trench; and forming a pad electrode on top of the Schottky contact metal.

Abstract: In one aspect, a semiconductor device may include a semiconductor substrate formed of silicon carbide; and an edge termination having a first metal layer and a second metal layer, wherein the first metal layer is deposited and patterned spacedly on the semiconductor substrate and the second metal layer is deposited and patterned onto at least a portion of the spaced first metal layer and onto the semiconductor substrate between said spaced first metal layer, and wherein the first metal layer comprises a high work function metal, while the second metal layer comprises a low work function metal. In one embodiment, the high work function metal includes Silver, Aluminum, Chromium, Nickel, and Gold; and the low work function metal includes Titanium and Nickel Silicide.

Abstract: A method for manufacturing a merged PiN Schottky (MPS) diode may include steps of providing a substrate having a first conductivity type; forming an epitaxial layer with the first conductivity type on top of the substrate; forming a plurality of regions with a second conductivity type under a top surface of the epitaxial layer; depositing and patterning a first Ohmic contact metal on the regions with the second conductivity type; depositing a Schottky contact metal on top of the entire epitaxial layer; and forming a second Ohmic contact metal on a backside of the substrate. In another embodiment, the step of forming a plurality of regions with a second conductivity type under a top surface of the epitaxial layer may include steps of depositing and patterning a mask layer on the epitaxial layer, implanting P-type dopant into the epitaxial layer, and removing the mask layer.

Abstract: In one aspect, a merged PiN Schottky (MPS) diode may include a silicon carbide substrate having a first conductivity type. The epitaxial layer with a first conductivity type was formed on the substrate, which has doping concentration lower than the substrate. A plurality of regions having the second conductivity type different from the first conductivity type are formed under the surface of the epitaxial layer. The Ohmic contact metal is formed on the region of the second conductivity type. The Schottky contact metal is placed on top of the entire epitaxial layer to form a Schottky junction. The Ohmic contact was formed by a cathode electrode on the back side of the substrate.

Abstract: A method for manufacturing a merged PiN Schottky (MPS) diode may include steps of providing a substrate having a first conductivity type; forming an epitaxial layer with the first conductivity type on top of the substrate; forming a plurality of regions with a second conductivity type under a top surface of the epitaxial layer; forming a plasma spreading layer; depositing and patterning a first Ohmic contact metal on the regions with the second conductivity type; depositing a Schottky contact metal on top of the entire epitaxial layer; and forming a second Ohmic contact metal on a backside of the substrate. In another embodiment, the step of forming a plurality of regions with a second conductivity type may include steps of depositing and patterning a mask layer on the epitaxial layer, implanting P-type dopant into the epitaxial layer, and removing the mask layer.