Patents by Inventor Zhengbin PANG

Zhengbin PANG has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11558315
    Abstract: The invention provides a converged network interface card, a message coding method and a message transmission method thereof. The converged network interface card comprises a PCIE host interface processing module, a high speed network card core logic, a crossbar switch XBAR, an Ethernet network card core logic, an Ethernet message dicing/slicing module, a physical layer, a high speed network/Ethernet message conversion module EoH, and a high speed network/Ethernet configurable network port. The invention supports customized high speed interconnection interface and a standard Ethernet interface on a set of network hardware, and supports three working modes on a set of physical hardware (high speed network mode, Ethernet mode and EoH mode transmitting Ethernet messages over the high speed network), implements seamless compatibility between the high speed network/Ethernet, and flexibly supports multimode applications such as scientific computing and cloud computing.
    Type: Grant
    Filed: December 2, 2020
    Date of Patent: January 17, 2023
    Assignee: NATIONAL UNIVERSITY OF DEFENSE TECHNOLOGY
    Inventors: Liquan Xiao, Junsheng Chang, Mingche Lai, Zhengbin Pang, Pingjing Lu, Zhang Luo, Yuan Li, Jianmin Zhang, Xingyun Qi, Jinbo Xu, Yan Sun, Dezun Dong
  • Patent number: 11265400
    Abstract: This invention discloses a multimode interconnection interface controller for a converged network, which comprises a SERDES element responsible for serial/parallel conversion, a LANE_TXCLK element responsible for generating a transmit clock, a SERDES initialization element responsible for link training and rate negotiation, and a PCS_EB coding element and an PCS_AF coding element responsible for physical layer coding of messages. The link training and rate negotiation are completed automatically via the shared SERDES initialization element. More universality and flexibility are provided for interconnection chip design by the PCS_EB coding element. The PCS_AF coding element is provided to reduce message penetration delay. The multimode interconnection interface controller is integrated in a single chip. Through flexible configuration, the single chip can meet transmission requirements of dedicated high speed networks and Ethernet networks.
    Type: Grant
    Filed: December 2, 2020
    Date of Patent: March 1, 2022
    Assignee: NATIONAL UNIVERSITY OF DEFENSE TECHNOLOGY
    Inventors: Mingche Lai, Liquan Xiao, Junsheng Chang, Pingjing Lu, Zhengbin Pang, Canwen Xiao, Lu Liu, Jijun Cao, Yi Dai, Jiaqing Xu, Qiang Wang, Fangxu Lv
  • Publication number: 20210367906
    Abstract: The invention provides a converged network interface card, a message coding method and a message transmission method thereof. The converged network interface card comprises a PCIE host interface processing module, a high speed network card core logic, a crossbar switch XBAR, an Ethernet network card core logic, an Ethernet message dicing/slicing module, a physical layer, a high speed network/Ethernet message conversion module EoH, and a high speed network/Ethernet configurable network port. The invention supports customized high speed interconnection interface and a standard Ethernet interface on a set of network hardware, and supports three working modes on a set of physical hardware (high speed network mode, Ethernet mode and EoH mode transmitting Ethernet messages over the high speed network), implements seamless compatibility between the high speed network/Ethernet, and flexibly supports multimode applications such as scientific computing and cloud computing.
    Type: Application
    Filed: December 2, 2020
    Publication date: November 25, 2021
    Applicant: NATIONAL UNIVERSITY OF DEFENSE TECHNOLOGY
    Inventors: Liquan XIAO, Junsheng CHANG, Mingche LAI, Zhengbin PANG, Pingjing LU, Zhang LUO, Yuan LI, Jianmin ZHANG, Xingyun QI, Jinbo XU, Yan SUN, Dezun DONG
  • Publication number: 20210360093
    Abstract: This invention discloses a multimode interconnection interface controller for a converged network, which comprises a SERDES element responsible for serial/parallel conversion, a LANE_TXCLK element responsible for generating a transmit clock, a SERDES initialization element responsible for link training and rate negotiation, and a PCS_EB coding element and an PCS_AF coding element responsible for physical layer coding of messages. The link training and rate negotiation are completed automatically via the shared SERDES initialization element. More universality and flexibility are provided for interconnection chip design by the PCS_EB coding element. The PCS_AF coding element is provided to reduce message penetration delay. The multimode interconnection interface controller is integrated in a single chip. Through flexible configuration, the single chip can meet transmission requirements of dedicated high speed networks and Ethernet networks.
    Type: Application
    Filed: December 2, 2020
    Publication date: November 18, 2021
    Applicant: NATIONAL UNIVERSITY OF DEFENSE TECHNOLOGY
    Inventors: Mingche LAI, Liquan XIAO, Junsheng CHANG, Pingjing LU, Zhengbin PANG, Canwen XIAO, Lu LIU, Jijun CAO, Yi DAI, Jiaqing XU, Qiang WANG, Fangxu LV