Patents by Inventor Zhengbo Cui

Zhengbo Cui has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12014058
    Abstract: A stacked memory includes a volatile memory die and a non-volatile memory die that are stacked together. The non-volatile memory die includes a non-volatile storage array and a peripheral circuit. The peripheral circuit includes a power integrity circuit and a signal integrity circuit. The power integrity circuit is configured to perform power integrity optimization on a power supply obtained from a lower-layer die and then transmit the power supply to an upper-layer die. The signal integrity circuit is configured to perform signal integrity optimization on a signal obtained from a lower-layer die and then transmit the signal to an upper-layer die.
    Type: Grant
    Filed: December 27, 2022
    Date of Patent: June 18, 2024
    Assignee: HUAWEI TECHNOLOGIES CO., LTD.
    Inventors: Weiliang Jing, Zhengbo Wang, Jingjie Cui
  • Patent number: 11972734
    Abstract: The present application provides a pixel driving circuit and a display panel. The pixel driving circuit includes a light emitting device, a voltage conversion module electrically connected to the light emitting device via a first node, a driving module electrically connected to the light emitting device via a second node, a data writing module electrically connected to the driving module via a fourth node, a first potential coupling module electrically connected to the second node and the third node, a second potential coupling module, and a first voltage terminal. Before the driving module controls a moment when the light emitting device starts to emit light, the voltage conversion module controls the potential of the first node to change from a first voltage to a second voltage, first potential coupling module couples potential of the third node, and second potential coupling module couples potential of the fourth node.
    Type: Grant
    Filed: March 30, 2023
    Date of Patent: April 30, 2024
    Assignee: Guangzhou China Star Optoelectronics Semiconductor Display Technology Co., Ltd.
    Inventor: Zhengbo Cui
  • Publication number: 20240072066
    Abstract: A display panel is provided, including a grounding signal wiring, driving chips, a driving chip input output signal wiring, and a power line. A grounding signal pin is connected to the grounding signal wiring. The driving chip input output signal wiring is configured to connect a stage-transfer signal input pin and a stage-transfer signal output pin of two adjacent driving chips. The grounding signal wiring, the driving chip input output signal wiring, and the power line are disposed in a same layer and do not intersect with each other.
    Type: Application
    Filed: March 29, 2022
    Publication date: February 29, 2024
    Inventors: Jing LIU, Hongzhao DENG, Zhengbo CUI, Hao CHEN
  • Publication number: 20240055418
    Abstract: A display panel is provided, including a power line, light-emitting lamp groups, partition channel wirings, driving chips, and a grounding signal wiring. The driving chips, the light-emitting lamp groups, and the partition channel wirings are disposed between the power line and the grouping signal wiring spaced apart. The driving chips are connected to the grounding signal wiring. The light-emitting lamp groups are connected to the power line. The partition channel wirings are connected to the light-emitting lamp groups. The power line, the grounding signal wiring, and the partition channel wirings are disposed in a same layer.
    Type: Application
    Filed: March 30, 2022
    Publication date: February 15, 2024
    Inventors: Jing LIU, Hongzhao DENG, Zhengbo CUI, Yichen BAI
  • Publication number: 20240027834
    Abstract: A backlight source and a display device are provided. The display panel includes the plurality of stacked metal sub-layers and the first passivation sub-layer and the second passivation sub-layer stacked. The first passivation sub-layer is disposed between the metal layer and the second passivation layer. Material of the first passivation sub-layer includes silicon nitride. The first passivation sub-layer covers the untidy area at the ends of the molybdenum-titanium alloy thin layer to avoid from detachment of the passivation layer, and meanwhile to solve the issues of simplifying the manufacturing process of the display panel, and to avoid from oxidation of the bonding pads.
    Type: Application
    Filed: December 17, 2021
    Publication date: January 25, 2024
    Applicant: TCL CHINA STAR OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventors: Jing Liu, Hongzhao Deng, Zhengbo Cui, Hao Chen
  • Publication number: 20240030273
    Abstract: A light source module and a display device include a substrate configured to have a plurality of light-emitting regions arranged in an array manner, each light-emitting region is provided with two light-emitting groups, each light-emitting group includes a plurality of light-emitting branches arranged side by side, and two driving chips are disposed in parallel between the two light-emitting groups; and single-layer layout wiring arranged on the substrate, wherein the single-layer layout wiring couples the driving chips within the light-emitting regions to each other and electrically connects each of the driving chips to the light-emitting branches within one of the light-emitting groups.
    Type: Application
    Filed: December 17, 2021
    Publication date: January 25, 2024
    Applicant: TCL CHINA STAR OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventors: Zhengbo Cui, Hongzhao Deng, Jing Liu, Hao Chen