Abstract: Methods, systems, and devices for techniques for firmware enhancement in memory devices are described. A memory system may include a volatile memory device and a non-volatile memory device, which may store a node address mapping. A host system in communication with the memory system may transmit a command instructing the memory system to transfer at least a portion of the node address mapping from the non-volatile memory device to the volatile memory device. The memory system may transmit a response to the command to the host system indicating a status associated with transferring the portion of the node address mapping.

Abstract: This disclosure relates to a bit line reading circuit, a memory, and an electronic device. An example bit line reading circuit includes a bit line connected to a ferroelectric memory cell. The bit line reading circuit further includes a reference line, a sense amplifier, and a precharge circuit. The sense amplifier and the precharge circuit are separately connected to the bit line and the reference line. The bit line reading circuit further includes a first switch connected to the bit line between the sense amplifier and the precharge circuit, and a second switch connected to the reference line between the sense amplifier and the precharge circuit.

Abstract: Embodiments of this disclosure relate to a vertical channel transistor structure. An example vertical channel transistor structure includes a stacked structure. The stacked structure includes a first metal layer, a first contact layer, an insulation dielectric layer, a second contact layer, a second metal layer, and a groove. The first contact layer is located between the first metal layer and the insulation dielectric layer, and the second contact layer is located between the second metal layer and the insulation dielectric layer. The groove penetrates the second metal layer, the second contact layer, the insulation dielectric layer, and the second contact layer. The groove is at least partially recessed into the first metal layer. The groove includes a semiconductor channel layer, a gate oxygen dielectric layer, and a gate.

Abstract: Methods, systems, and devices for pre-operation for application to boost firmware performance are described. A host system may notify a memory system of a logical block address range corresponding to an upcoming access operation. The memory system may use the logical block address range to load an associated portion of a logical-to-physical mapping from a non-volatile memory device to a volatile memory device prior to receiving a command to perform the access operation. Accordingly, after the host system issues the command for the memory system to perform the access operation, the memory system may perform the access operation faster as the memory system has already loaded relevant portions of the logical-to-physical mapping associated with the access operation.

Abstract: Methods, systems, and devices for techniques for firmware enhancement in memory devices are described. A memory system may include a volatile memory device and a non-volatile memory device, which may store a node address mapping. A host system in communication with the memory system may transmit a command instructing the memory system to transfer at least a portion of the node address mapping from the non-volatile memory device to the volatile memory device. The memory system may transmit a response to the command to the host system indicating a status associated with transferring the portion of the node address mapping.

Abstract: This disclosure discloses a memory, a memory use method, a memory manufacturing method, and an electronic device. The memory includes a control layer and at least one storage layer stacked on the control layer. The storage layer includes a plurality of storage channels, and each storage channel includes an independent data interface bus. The control layer includes a plurality of controllers and a plurality of user interfaces, the controller is configured to access data stored in a storage channel connected to the controller. The plurality of controllers are connected to the data interface buses of the plurality of storage channels in one-to-one correspondence. A quantity of user interfaces is the same as a quantity of user storage channels that can be invoked by a user. The quantity of user interfaces is less than a quantity of controllers.

Abstract: This disclosure relates to storage circuits, memories, and storage apparatuses. An example memory includes a storage circuit. The storage circuit includes a first bank, a second bank, a first global data amplifier, global input/output (GIO) routing, and an interface circuit. The first bank and the second bank share the first global data amplifier, and the first global data amplifier is coupled to the interface circuit through the GIO.

Abstract: A stacked memory includes a volatile memory die and a non-volatile memory die that are stacked together. The non-volatile memory die includes a non-volatile storage array and a peripheral circuit. The peripheral circuit includes a power integrity circuit and a signal integrity circuit. The power integrity circuit is configured to perform power integrity optimization on a power supply obtained from a lower-layer die and then transmit the power supply to an upper-layer die. The signal integrity circuit is configured to perform signal integrity optimization on a signal obtained from a lower-layer die and then transmit the signal to an upper-layer die.

Abstract: A ferroelectric memory includes a substrate and a plurality of memory cells formed on the substrate. Each memory cell includes a transistor and a plurality of ferroelectric capacitors. In other words, each memory cell includes at least two ferroelectric capacitors to implement multi-bit data storage. The transistor and the plurality of ferroelectric capacitors are arranged in a first direction perpendicular to the substrate. Any ferroelectric capacitor includes a first electrode layer, a second electrode layer, and a ferroelectric layer formed between the first electrode layer and the second electrode layer. The first electrode layers of every two adjacent ferroelectric capacitors of the plurality of ferroelectric capacitors are in contact, to form a shared first electrode layer that extends in the first direction.

Abstract: A memory comprises a substrate and a plurality of storage units formed on the substrate. Each of the storage units includes a transistor and a capacitor electrically connected to the transistor. The transistor includes a gate, a semiconductor layer, a first electrode, a second electrode, and a gate dielectric layer. The first electrode and the second electrode are arranged in a first direction. The gate is located between the first electrode and the second electrode. The semiconductor layer is located on one of two opposite sides of the gate in a second direction. The semiconductor layer is electrically connected separately to the first electrode and the second electrode, the gate and the semiconductor layer are isolated from each other by the gate dielectric layer, and the second direction is a direction parallel to the substrate.

Abstract: Methods, systems, and devices for techniques for firmware enhancement in memory devices are described. A memory system may include a volatile memory device and a non-volatile memory device, which may store a node address mapping. A host system in communication with the memory system may transmit a command instructing the memory system to transfer at least a portion of the node address mapping from the non-volatile memory device to the volatile memory device. The memory system may transmit a response to the command to the host system indicating a status associated with transferring the portion of the node address mapping.

Abstract: A thin-film transistor (TFT) includes a gate, a first electrode, a second electrode, a first dielectric layer, a second dielectric layer, and a semiconductor layer. The gate includes a gate base located at a top portion and a gate body extending from the gate base to a bottom portion. The first electrode is located at the bottom portion. The second electrode is located between the first electrode and the gate base. The first dielectric layer is disposed between the second electrode and the first electrode, and the first dielectric layer is configured to separate the first electrode from the second electrode. The second dielectric layer covers a surface of the gate base and a surface of the gate body. The semiconductor layer is disposed along a side surface of the gate body, and the second dielectric layer separates the semiconductor layer from the gate.

Abstract: A storage controller is coupled to a memory, and the memory includes a first storage area and a second storage area. The storage controller includes a data migration circuit and a data operation determining circuit. The data migration circuit is configured to generate a migration signal, to migrate data in the first storage area to the second storage area. In a process in which the data migration circuit migrates all the data in the first storage area to the second storage area, the data operation determining circuit is configured to: receive and monitor a data operation signal input to the memory, and output a data migration failure signal when detecting that the data operation signal is a data modify signal with respect to the first storage area.

Abstract: A storage apparatus includes a first memory disposed in a first die and configured to store data, a second memory disposed in a second die and configured to store an error correcting code corresponding to the data. The error correcting code may be used to perform data protection on the data. A storage controller is configured to write the data into the first memory, and read the data from the first memory.

Abstract: A stacked memory includes a volatile memory die and a non-volatile memory die that are stacked together. The non-volatile memory die includes a non-volatile storage array and a peripheral circuit. The peripheral circuit includes a power integrity circuit and a signal integrity circuit. The power integrity circuit is configured to perform power integrity optimization on a power supply obtained from a lower-layer die and then transmit the power supply to an upper-layer die. The signal integrity circuit is configured to perform signal integrity optimization on a signal obtained from a lower-layer die and then transmit the signal to an upper-layer die.

Abstract: A storage controller is coupled to a memory, and the memory includes a first storage area and a second storage area. The storage controller includes a data migration circuit and a data operation determining circuit. The data migration circuit is configured to generate a migration signal, to migrate data in the first storage area to the second storage area. In a process in which the data migration circuit migrates all the data in the first storage area to the second storage area, the data operation determining circuit is configured to: receive and monitor a data operation signal input to the memory, and output a data migration failure signal when detecting that the data operation signal is a data modify signal with respect to the first storage area.

Abstract: A mobile computing device captures an image of an identification code on an object that identifies the object, extracts the code from the image, and forwards the code and a user ID to a server, which responds with digital key when the user ID has been verified. The mobile computing device converts the digital key into a pulsed light sequence that represents the digital key. An unlocking device attached to the object detects the pulsed light sequence, recovers the digital key from the pulsed light sequence, compares the recovered digital key to a pre-stored digital key, and unlocks the device when the recovered digital key matches the pre-stored digital key.

Abstract: False authentication that is obtained by using a photographic image to impersonate a real human being when being photographed for authentication is prevented by photographing a user's face while illuminated by two different patterns on a display screen to obtain two different images, determining a difference between the two different images to obtain a difference image, and then comparing the difference image to previous images to determine if a real human being is attempting authentication.

Abstract: The complex operation and low control efficiency in controlling home devices, such as lights, televisions, and curtains, is reduced with a control system that senses the presence and any actions, such as hand gestures or speech, of a user in a predetermined space. In addition, the control system identifies a device to be controlled, and the command to be transmitted to the device in response to a sensed action.