Abstract: An array substrate, a display panel and a display device are provided. The array substrate includes a display region and a border region. The border region includes a first border and a second border arranged oppositely in a first direction. The display region includes a hollowed-out region, a second sub-display region and a primary display region, a data drive port located in the border region and data lines extended in the first direction. The data lines include second data lines located in the second sub-display region and auxiliary data lines located in the primary display region. The data drive port provides a data signal to sub-pixels in the second sub-display region through the auxiliary data lines and the second data lines.

Abstract: A method for manufacturing an array substrate, and an array substrate, a display panel and a display device are provided. The method may include: forming, on one side of a substrate, a gate electrode layer, a gate insulation layer and a semiconductor layer, wherein the gate electrode layer has a same pattern as the semiconductor layer; forming an etching stop layer on the semiconductor layer; forming a first, second hole and third through holes by patterning the etching stop layer; forming a source electrode layer and a drain electrode layer on the etching stop layer, wherein the source electrode layer is electrically connected with the semiconductor layer via the first through hole, and the drain electrode layer is electrically connected with the semiconductor layer via the second through hole; forming an active layer by etching the semiconductor layer at the location corresponding to the third through hole.

Abstract: An array substrate, a display panel and a display device are provided. The array substrate includes a display region and a border region. The border region includes a first border and a second border arranged oppositely in a first direction. The display region includes a hollowed-out region, a second sub-display region and a primary display region, a data drive port located in the border region and data lines extended in the first direction. The data lines include second data lines located in the second sub-display region and auxiliary data lines located in the primary display region. The data drive port provides a data signal to sub-pixels in the second sub-display region through the auxiliary data lines and the second data lines.

Abstract: A method for manufacturing an array substrate, and an array substrate, a display panel and a display device are provided. The method may include: forming, on one side of a substrate, a gate electrode layer, a gate insulation layer and a semiconductor layer, wherein the gate electrode layer has a same pattern as the semiconductor layer; forming an etching stop layer on the semiconductor layer; forming a first, second hole and third through holes by patterning the etching stop layer; forming a source electrode layer and a drain electrode layer on the etching stop layer, wherein the source electrode layer is electrically connected with the semiconductor layer via the first through hole, and the drain electrode layer is electrically connected with the semiconductor layer via the second through hole; forming an active layer by etching the semiconductor layer at the location corresponding to the third through hole.

Abstract: A method for manufacturing an array substrate, and an array substrate, a display panel and a display device are provided. The method may include: forming, on one side of a substrate, a gate electrode layer, a gate insulation layer and a semiconductor layer, wherein the gate electrode layer has a same pattern as the semiconductor layer; forming an etching stop layer on the semiconductor layer; forming a first, second hole and third through holes by patterning the etching stop layer; forming a source electrode layer and a drain electrode layer on the etching stop layer, wherein the source electrode layer is electrically connected with the semiconductor layer via the first through hole, and the drain electrode layer is electrically connected with the semiconductor layer via the second through hole; forming an active layer by etching the semiconductor layer at the location corresponding to the third through hole.

Abstract: A display substrate, a display device and a method to identify a display device are provided. The display substrate comprises a display region and a periphery region. The periphery region comprises a plurality of first bonding pads electrically connected to metal wires disposed at the display region and a plurality of second bonding pads including at least two identification bonding pads. The at least two identification bonding pads are electrically connected to voltage-level signal lines respectively, and are labeled with identify information according to voltage-level signals provide by the voltage-level signal lines.

Abstract: A display substrate, a display device and a method to identify a display device are provided. The display substrate comprises a display region and a periphery region. The periphery region comprises a plurality of first bonding pads electrically connected to metal wires disposed at the display region and a plurality of second bonding pads including at least two identification bonding pads. The at least two identification bonding pads are electrically connected to voltage-level signal lines respectively, and are labeled with identify information according to voltage-level signals provide by the voltage-level signal lines.

Abstract: A display substrate, a display device and a method to identify a display device are provided. The display substrate comprises a display region and a periphery region. The periphery region comprises a plurality of first bonding pads electrically connected to metal wires disposed at the display region and a plurality of second bonding pads including at least two identification bonding pads. The at least two identification bonding pads are electrically connected to voltage-level signal lines respectively, and are labeled with identify information according to voltage-level signals provide by the voltage-level signal lines.

Abstract: The present disclosure discloses an array substrate, touch display panel and touch display device. The array substrate comprises a substrate, a display region and a non-display region surrounding the display region. A driver chip is provided in the non-display region. The display region comprises a plurality of data lines. Each of the plurality of data lines is electrically connected to the driver chip via a respective one of a plurality of first connection lines; and a plurality of touch electrode blocks. The plurality of touch electrode blocks are electrically connected to the driver chip via a plurality of touch signal lines. In the non-display region, the plurality of touch signal lines are not overlapped with the plurality of first connection lines in a direction perpendicular to the substrate.

Abstract: A display substrate, a display device and a method to identify a display device are provided. The display substrate comprises a display region and a periphery region. The periphery region comprises a plurality of first bonding pads electrically connected to metal wires disposed at the display region and a plurality of second bonding pads including at least two identification bonding pads. The at least two identification bonding pads are electrically connected to voltage-level signal lines respectively, and are labeled with identify information according to voltage-level signals provide by the voltage-level signal lines.

Abstract: A method for manufacturing an array substrate, and an array substrate, a display panel and a display device are provided. The method may include: forming, on one side of a substrate, a gate electrode layer, a gate insulation layer and a semiconductor layer, wherein the gate electrode layer has a same pattern as the semiconductor layer; forming an etching stop layer on the semiconductor layer; forming a first, second hole and third through holes by patterning the etching stop layer; forming a source electrode layer and a drain electrode layer on the etching stop layer, wherein the source electrode layer is electrically connected with the semiconductor layer via the first through hole, and the drain electrode layer is electrically connected with the semiconductor layer via the second through hole; forming an active layer by etching the semiconductor layer at the location corresponding to the third through hole.