Abstract: A distributed data acquisition system comprising multiple, physically unconnected, data acquisition units that can be in wireless communication with a remote host, timestamps measurement data with sub-microsecond time base accuracy of sampling clock relative to an absolute timeframe. Each unit has a GPS receiver for deriving an absolute time. An analog-to-digital converter samples measurement data using a sampling clock. A hardware logic circuit, such as a field programmable gate array, associates batches of the measurement data with corresponding timestamps representing the current absolute time. A time offset bias may be compensated by a comparison of timestamps with nominal time based on start time and nominal sampling rate. Additionally, the sampling clock may be synchronized using time pulses from the GPS receiver. An initial start of ADC sampling by all data acquisition units may be also synchronized.

Abstract: A method uses a distributed data acquisition system with multiple, physically unconnected, data acquisition units, that can be in wireless communication with a remote host, to timestamp measurement data with sub-microsecond time base accuracy of sampling clock relative to an absolute timeframe. A current absolute time is derived from messages received from a satellite radio beacon positioning system (GPS). Measurement data is sampled by each unit at a specified sampling rate. Using hardware logic, batches of sampled data are associated with corresponding timestamps representing the absolute time at which the data was sampled. Data and timestamps may be transmitted to the host. A time offset bias is compensated by comparing timestamps against a nominal time based on start time and nominal sampling rate. The sampling clock rate may be disciplined using time pulses from the GPS receiver. An initial start of data sampling by all units can also be synchronized.

Abstract: A method uses a distributed data acquisition system with multiple, physically unconnected, data acquisition units, that can be in wireless communication with a remote host, to timestamp measurement data with sub-microsecond time base accuracy of sampling clock relative to an absolute timeframe. A current absolute time is derived from messages received from a satellite radio beacon positioning system (GPS). Measurement data is sampled by each unit at a specified sampling rate. Using hardware logic, batches of sampled data are associated with corresponding timestamps representing the absolute time at which the data was sampled. Data and timestamps may be transmitted to the host. A time offset bias is compensated by comparing timestamps against a nominal time based on start time and nominal sampling rate. The sampling clock rate may be disciplined using time pulses from the GPS receiver. An initial start of data sampling by all units can also be synchronized.

Abstract: A distributed data acquisition system comprising multiple, physically unconnected, data acquisition units that can be in wireless communication with a remote host, timestamps measurement data with sub-microsecond time base accuracy of sampling clock relative to an absolute timeframe. Each unit has a GPS receiver for deriving an absolute time. An analog-to-digital converter samples measurement data using a sampling clock. A hardware logic circuit, such as a field programmable gate array, associates batches of the measurement data with corresponding timestamps representing the current absolute time. A time offset bias may be compensated by a comparison of timestamps with nominal time based on start time and nominal sampling rate. Additionally, the sampling clock may be synchronized using time pulses from the GPS receiver. An initial start of ADC sampling by all data acquisition units may be also synchronized.

Abstract: An integrated controller for an environmental testing system simultaneously controls and synchronizes vibration, temperature, and humidity in an environment test chamber over a specified reliability test duration, and performs condition-based measurement and processing of vibration data obtained from the environment test chamber for one or more specified trigger conditions. The controller executes a combined run schedule using a single internal clock and a hardware processor, to generate parameter control commands for the environment test chamber that remain synchronized to the single internal clock over the duration of a test, even one that lasts for weeks or months. This permits multi-variate processing of measured instantaneous values of temperature, humidity, and vibration to obtain, e.g., condition-dependent vibration power spectra and averages for available conditions of temperature, humidity, or both.

Abstract: A plurality of measurement devices have analog sensors that measure the dynamic signals of physical events, sample the data into digital format with time synchronized clocks and generate time stamped Ethernet messages that are sent to a remote host. The remote host has a master clock that evaluates decoded time stamped messages from the measurement devices and sends back a message with a time correction error signal relative to the master clock. This feedback signal is used by the measurement devices to correct a local clock for data sampling and new message generation. Eight wire cable and associated connectors are used to handle three channels of traffic, with four wires dedicated to Ethernet messages as one channel, another two wires dedicated to reset and other commands as a second channel and another two wires to transmit power from the host to the measurement devices as a third channel.

Abstract: A plurality of measurement devices have analog sensors that measure the dynamic signals of physical events, sample the data into digital format with time synchronized clocks and generate time stamped Ethernet messages that are sent to a remote host. The remote host has a master clock that evaluates decoded time stamped messages from the measurement devices and sends back a message with a time correction error signal relative to the master clock. This feedback signal is used by the measurement devices to correct a local clock for data sampling and new message generation. Eight wire cable and associated connectors are used to handle three channels of traffic, with four wires dedicated to Ethernet messages as one channel, another two wires dedicated to reset and other commands as a second channel and another two wires to transmit power from the host to the measurement devices as a third channel.

Abstract: In a data acquisition instrument with dual A/D converters in each measurement channel, phase corrections between the paths are computed using a locally generated calibration signal. The calibration signal goes through dual paths simultaneously and is stitched into a single signal for analysis by a processor running a Fourier transform where phase differences are easily identified and used to establish a phase correction signal applied to a single master clock supplying clock signals to both paths. A switch allows the calibration signal to be applied to each channel or to no channels when actual data is being collected.

Abstract: A circuit and method of analog data acquisition synchronization from an analog sensor in multiple channels associated with a USB hub. An analog to digital converter connected to the sensor that is part of a USB device has a time and phase corrected sampling clock that is referenced to a start-of-frame traffic signal with a preconfigured message indicating a time offset or delay seen upstream through a USB port. A plurality of similar devices are autonomously synchronized by the same message for multi-channel data acquisition by a locally generated trigger signal that allows a preset amount of delay set by the message. An accelerometer is a preferred sensor for such multi-channel data acquisition.

Abstract: A circuit and method of analog data acquisition synchronization from an analog sensor in multiple channels associated with a USB hub. An analog to digital converter connected to the sensor that is part of a USB device has a time and phase corrected sampling clock that is referenced to a start-of-frame traffic signal with a preconfigured message indicating a time offset or delay seen upstream through a USB port. A plurality of similar devices are autonomously synchronized by the same message for multi-channel data acquisition by a locally generated trigger signal that allows a preset amount of delay set by the message. An accelerometer is a preferred sensor for such multi-channel data acquisition.

Abstract: In a data acquisition instrument with dual A/D converters in each measurement channel, phase corrections between the paths are computed using a locally generated calibration signal. The calibration signal goes through dual paths simultaneously and is stitched into a single signal for analysis by a processor running a Fourier transform where phase differences are easily identified and used to establish a phase correction signal applied to a single master clock supplying clock signals to both paths. A switch allows the calibration signal to be applied to each channel or to no channels when actual data is being collected.

Abstract: A circuit and method of analog data acquisition synchronization from an analog sensor in multiple channels associated with a USB hub. An analog to digital converter connected to the sensor that is part of a USB device has a time and phase corrected sampling clock that is referenced to a start-of-frame traffic signal with a preconfigured message indicating a time offset or delay seen upstream through a USB port. A plurality of similar devices are autonomously synchronized by the same message for multi-channel data acquisition by a locally generated trigger signal that allows a preset amount of delay set by the message. An accelerometer is a preferred sensor for such multi-channel data acquisition.

Abstract: A signal analysis system is provided that includes master DSP circuitry, slave DSP circuitry, a LVDS bus, wherein the LVDS bus couples the master DSP circuitry to the slave DSP circuitry, and a USB interface, wherein the USB interface is coupled to the master DSP circuit.

Abstract: An interface includes a slave digital signal processor (DSP) and a master DSP connected to the slave DSP through a communications port. The master DSP includes a memory; and a direct memory access (DMA) to the memory. A field programmable gate array (FPGA) is connected to the master DSP. The FPGA includes a dual port random access memory (RAM) in communication with the DMA. A universal serial bus (USB) interface is connected to the FPGA through the dual port RAM.