Abstract: An interleaver and method for interleaving are provided, where initialization values are pre-calculated and stored in memory. In one implementation, the method of interleaving includes: calculating in advance an initial value of at least one parameter for use by logic circuitry to initialize interleaving operation; storing the initial value of the at least one parameter as a stored initial value of the at least one parameter; and using the stored initial value of the at least one parameter with the logic circuitry to generate interleaved order positions for the set of data items. In one implementation, the interleaver includes: logic circuitry for generating interleaved order positions for the set of data items and memory coupled to the logic circuitry for holding an initial value of at least one parameter for use by the logic circuitry to initialize interleaving operation.

Abstract: A state metric calculator for calculating state metrics of stages in a trellis of a sequence estimation technique is described. The calculator has a processing path containing operations needed for calculating a state metric of a trellis stage from state metrics of an earlier trellis stage. One or more data stores are located in the processing path to divide the path into separate sections. The sections can then operate on the production of different state metrics to one another in, if desired, the same clock cycle.

Abstract: A programmable integrated circuit device can be configured as a cascaded integrator-comb (CIC) filter. In order to take advantage of Hogenauer pruning to configure the CIC filter efficiently, a software tool for configuring the device can be provided in which the Fj terms for Hogenauer pruning have been calculated in advance for all possible user parameters supported by the tool. To configure a CIC filter, the user enters the parameters in the tool, which then looks up the Fj terms corresponding to those parameters and completes the calculation of the Bj terms for Hogenauer pruning. Because the calculation of the Fj terms is the most time-consuming step in calculating of the Bj terms, pre-calculation of the Fj terms, which can be done just once by the provider of the tool, allows end users to calculate the Bj terms in reasonable periods of time, making Hogenauer pruning available to end users.

Abstract: A sequence estimator is described. In one embodiment, the sequence estimator includes a plurality of maximum a posteriori probability (MAP) decoding engines each arranged to process a series of windows of a transmitted signal where state metrics produced for an end of one window by one decoding engine are re-used for the initialization of a state metric calculation process performed by another decoding engine on another window of the signal.

Abstract: Interleaving and deinterleaving schemes for operating in parallel on sections of a data block to load memories with respective segments of a reordered version of the block, in a manner which can avoid memory conflicts.

Abstract: Interleaving in which functions relating final and original positions are implemented with low complexity using inequalities based on the functions.

Abstract: A state metric calculator for calculating state metrics of stages in a trellis of a sequence estimation technique is described. The calculator has a processing path containing operations needed for calculating a state metric of a trellis stage from state metrics of an earlier trellis stage. One or more data stores are located in the processing path to divide the path into separate sections. The sections can then operate on the production of different state metrics to one another in, if desired, the same clock cycle.

Abstract: While debugging, a user chooses an incremental recompile. Internal signals of interest are selected and output pins are optionally reserved. An incremental recompile of the compiled design includes compiling a routing from each internal signal to an output pin. The technology-mapped netlist and placing and routing information corresponding to an original compiled design are saved into a database during full compilation. During debugging, an incremental compiler retrieves this information to build the original routing netlist. The database building, logic synthesis and technology mapping stages may be skipped. New connections are added, fitted to the device, and then the final routing netlist is output into a programming output file (POF) in a form suitable for programming the PLD. The user views the internal signals at the output pins chosen. The user may iterate through this process many times in order to debug the PLD. The debugging assignments may be deleted.

Abstract: While debugging, a user chooses an incremental recompile. Internal signals of interest are selected and output pins are optionally reserved. An incremental recompile of the compiled design includes compiling a routing from each internal signal to an output pin. The technology-mapped netlist and placing and routing information corresponding to an original compiled design are saved into a database during full compilation. During debugging, an incremental compiler retrieves this information to build the original routing netlist. The database building, logic synthesis and technology mapping stages may be skipped. New connections are added, fitted to the device, and then the final routing netlist is output into a programming output file (POF) in a form suitable for programming the PLD. The user views the internal signals at the output pins chosen. The user may iterate through this process many times in order to debug the PLD. The debugging assignments may be deleted.