Abstract: An array substrate has a hole-opening region, a display region surrounding the hole-opening region, and a hole-peripheral region located between the hole-opening region and the display region. The array substrate includes a substrate and a driving circuit layer located on the substrate. The driving circuit layer includes a constant-voltage conductive ring and a plurality of signal lines. At least some of the plurality of signal lines are target signal lines. The target signal lines each include a lead portion and a winding portion connected thereto. The lead portion extends from the hole-peripheral region to the display region, and the winding portion is located in the hole-peripheral region and is disposed along an edge of the hole-opening region. The constant-voltage conductive ring is located in the hole-peripheral region and is disposed around the hole-opening region. The winding portion is located between the constant-voltage conductive ring and the hole-opening region.

Abstract: A display substrate includes: a base substrate and a plurality of sub-pixels arranged on the base substrate, the sub-pixel include a sub-pixel driving circuit, the sub-pixel driving circuit includes: a first transistor, a driving transistor, and a first conductive connection portion; a first electrode of the first transistor is coupled to a second electrode of the driving transistor, a second electrode of the first transistor and a first end portion of the first conductive connection portion are arranged at different layers, the second electrode of the first transistor and the first end portion of the first conductive connection portion are coupled through a via hole; a second end portion of the first conductive connection portion is coupled to a gate electrode of the driving transistor.

Abstract: A display substrate includes: a base substrate and a plurality of sub-pixels arranged on the base substrate, the sub-pixel include a sub-pixel driving circuit, the sub-pixel driving circuit includes: a first transistor, a driving transistor, and a first conductive connection portion; a first electrode of the first transistor is coupled to a second electrode of the driving transistor, a second electrode of the first transistor and a first end portion of the first conductive connection portion are arranged at different layers, the second electrode of the first transistor and the first end portion of the first conductive connection portion are coupled through a via hole; a second end portion of the first conductive connection portion is coupled to a gate electrode of the driving transistor.

Abstract: A display substrate includes a base substrate, multiple light emitting elements, and multiple pixel circuits. The multiple light emitting elements include multiple groups of light emitting elements. At least one of the multiple groups of light emitting elements includes multiple first region light emitting elements located in a first display region and multiple second region light emitting elements located in a second display region. The multiple pixel circuits include multiple groups of pixel circuits. At least one of the multiple groups of pixel circuits includes multiple first type pixel circuits and multiple second type pixel circuits. The multiple first region light emitting elements at least include multiple first light emitting elements emitting light in a first color and multiple second light emitting elements emitting light in a second color. The multiple first type pixel circuits include multiple first pixel circuits and multiple second pixel circuits.

Abstract: A display substrate and a display apparatus are provided. The display substrate includes a base substrate including a display region and a peripheral region; a driving functional layer on one side of the base substrate and including pixel driving circuits in the display region and arranged in an array along a first and second directions intersecting with each other; a first conductive layer on a side of the driving functional layer away from the base substrate and including first power lines for providing a first operating voltage; a first planarization layer and a second conductive layer between the driving functional layer and the first conductive layer. The first planarization layer is between the first and second conductive layers, and the second conductive layer includes a first conductive pattern electrically connected in parallel with a corresponding first power line through a first via in the first planarization layer.

Abstract: A display substrate and a display device are provided. The display substrate includes a base substrate and a plurality of pixel circuits, the plurality of pixel circuits are arranged on the base substrate in an array, the plurality of pixel circuits include a plurality of active patterns, each of the plurality of active patterns extends along a first direction, the plurality of active patterns are arranged along a second direction, adjacent active patterns are spaced apart from each other in the second direction, and at least one of the plurality of active patterns comprises at least one disconnection position to form a plurality of active sub-patterns independent of each other.

Abstract: Provided are a display substrate and a display device. The display substrate includes a base substrate, and a driving circuit layer and a light-emitting device layer on the base substrate. The display substrate includes a light-transmitting display area and a normal display area, the normal display area surrounds at least a portion of the light-transmitting display area. The normal display area includes multiple normal driving circuits and multiple dummy driving circuits; some dummy driving circuit are used for driving light-emitting devices located in the light-transmitting display area. The display substrate further includes multiple normal data lines coupled to the normal driving circuits; at least one normal data line is coupled to a data signal input terminal through a data lead; an orthographic projection of the data lead onto the base substrate at least partially overlaps an orthographic projection of the dummy driving circuit onto the base substrate.

Abstract: A display substrate includes: a base substrate and a plurality of sub-pixels arranged on the base substrate, the sub-pixel include a sub-pixel driving circuit, the sub-pixel driving circuit includes: a first transistor, a driving transistor, and a first conductive connection portion; a first electrode of the first transistor is coupled to a second electrode of the driving transistor, a second electrode of the first transistor and a first end portion of the first conductive connection portion are arranged at different layers, the second electrode of the first transistor and the first end portion of the first conductive connection portion are coupled through a via hole; a second end portion of the first conductive connection portion is coupled to a gate electrode of the driving transistor.

Abstract: An array substrate is provided. The array substrate includes K number of columns of first pads. A respective first pad is connected to an anode of a light emitting element, a second electrode of a fifth transistor, and a second electrode of a sixth transistor. The K number of columns of first pads include a plurality of first-first pads in (2k-1)-th columns of the K columns and a plurality of second-first pads in (2k)-th columns of the K columns. A respective first-first pad and a respective second-first pad have different average line widths.

Abstract: A display panel and a display device are disclosed. The display panel includes display area and a peripheral area surrounding the display area. The peripheral area includes a first peripheral area located at a side of the display area, the first peripheral area has a cell test area for arranging a cell test unit, the display panel has a first edge, and the first edge is located at a side of the first peripheral area away from the display area. The display panel is provided with a reference power bus and a touch signal line, and in the first peripheral area, the reference power bus has a reference power bus protrusion.

Abstract: A display substrate and a display device are provided. The display substrate includes a first display area and a second display area. The first display area includes first light-emitting units and first pixel circuits, and the first pixel circuits are electrically connected with the first light-emitting units; the second display area includes second light-emitting units and second pixel circuits, and the second pixel circuits are electrically connected with the second light-emitting units; the first light-emitting units are electrically connected with first pixel circuits through first connection traces; the first display area includes a first region and a second region, the first region is located between the second region and the second display area, and a line width of at least one first connection trace located in the second region is smaller than a line width of at least one first connection trace located in the first region.

Abstract: An array substrate is provided. The array substrate includes K number of columns of first pads. A respective first pad is connected to an anode of a light emitting element, a second electrode of a fifth transistor, and a second electrode of a sixth transistor. The K number of columns of first pads include a plurality of first-first pads in (2k-1)-th columns of the K columns and a plurality of second-first pads in (2k)-th columns of the K columns. A respective first-first pad and a respective second-first pad have different average line widths.

Abstract: An array substrate is provided. The array substrate includes a plurality of pixel driving circuits configured to drive light emission in a plurality of subpixels; at least one dummy circuit incapable of driving light emission; and a plurality of voltage supply lines configured to provide a voltage. The voltage is provided to a second capacitor electrode of at least one pixel driving circuit of the plurality of pixel driving circuits, and is provided to both capacitor electrodes of the at least one dummy circuit.

Abstract: Provided are a display substrate and a display device. The display substrate includes a base substrate, and a driving circuit layer and a light-emitting device layer on the base substrate. The display substrate includes a light-transmitting display area and a normal display area, the normal display area surrounds at least a portion of the light-transmitting display area. The normal display area includes multiple normal driving circuits and multiple dummy driving circuits; some dummy driving circuit are used for driving light-emitting devices located in the light-transmitting display area. The display substrate further includes multiple normal data lines coupled to the normal driving circuits; at least one normal data line is coupled to a data signal input terminal through a data lead; an orthographic projection of the data lead onto the base substrate at least partially overlaps an orthographic projection of the dummy driving circuit onto the base substrate.

Abstract: The present disclosure provides a display substrate, a method for manufacturing the same, and a display device. The display substrate comprises a base substrate, at least four metal layers laminated in a direction away from the base substrate, a display region, a frame region arranged on at least one side of the display region, and a plurality of data lines are at least partially arranged in the display region, wherein, an insulating layer is provided between two adjacent the metal layers; in the frame region, the metal layer comprises a plurality of data signal leads; the data signal leads are coupled to the corresponding data lines; and orthographic projections of the data signal leads of at least two of the metal layers on the base substrate are at least partially overlapped.

Abstract: An array substrate is provided. The array substrate includes a plurality of first reset signal lines configured to provide a plurality of first reset signals, a plurality of second reset signal lines configured to provide a plurality of second reset signals, a plurality of third reset signal lines, and a plurality of first connecting lines. A respective first reset signal line is connected to a row of first connecting lines, which in turn are connected to source electrodes of first reset transistors in a row of subpixels, respectively. The plurality of second reset signal lines and the plurality of third reset signal lines form an interconnected reset signal supply network. A respective second reset signal line is connected to one or more of the plurality of third reset signal lines. A respective third reset signal line is connected to one or more of the plurality of second reset signal lines.

Abstract: A display substrate includes: a base substrate and a plurality of sub-pixels arranged on the base substrate, the sub-pixel include a sub-pixel driving circuit, the sub-pixel driving circuit includes: a first transistor, a driving transistor, and a first conductive connection portion; a first electrode of the first transistor is coupled to a second electrode of the driving transistor, a second electrode of the first transistor and a first end portion of the first conductive connection portion are arranged at different layers, the second electrode of the first transistor and the first end portion of the first conductive connection portion are coupled through a via hole; a second end portion of the first conductive connection portion is coupled to a gate electrode of the driving transistor.

Abstract: Provided is a display panel. The display panel includes: a base substrate, including a first display region and a second display region at least partially surrounding the first display region; a drive circuit layer on a side of the base substrate, wherein the drive circuit layer includes a plurality of first pixel circuits and a plurality of second pixel circuits that are disposed in the second display region; and a first electrode layer, at least including a plurality of first-type electrode patterns, wherein the plurality of first-type electrode patterns include a plurality of first electrode patterns in the first display region and a plurality of second electrode patterns in the second display region; wherein at least two first electrode patterns are connected to the first pixel circuit, and at least two second electrode patterns are connected to the second pixel circuit.

Abstract: A display substrate, a display panel, and a display device are provided. The display substrate includes: a base substrate; a plurality of sub-pixels in the display pixel region, wherein each sub-pixel includes a pixel driving circuit; a plurality of first dummy sub-pixel structures on the base substrate and in the first dummy pixel region, wherein at least one first dummy sub-pixel structure includes a compensation capacitor; and a plurality of scan signal lines arranged on the base substrate and configured to transmit a scan signal to the pixel driving circuit. At least one scan signal line extends through the display pixel region and the first dummy pixel region, and the at least one scan signal line is electrically connected to the pixel driving circuit of each sub-pixel in a row of sub-pixels and is further electrically connected to the compensation capacitor of the at least one first dummy sub-pixel structure.

Abstract: A display substrate and a display panel, the display substrate includes a base substrate and a plurality of sub-pixels, a plurality of data lines and a plurality of data wirings located on the base substrate. The plurality of data wirings includes a first data wiring, a second data wiring and a third data wiring that are periodically arranged. The first data wiring is located in a first conductor layer. The second data wiring is located in a second conductor layer. The third data wiring is located in a third conductor layer. An orthographic projection of a part of at least one first data wiring on the base substrate overlaps with an orthographic projection of a part of at least one third data wiring on the base substrate.