Abstract: A semiconductor device includes a plurality of memory blocks. Each memory block includes a memory deck including interleaved first conductor layers and first dielectric layers, and a separation structure extending to separate two adjacent memory blocks. Each separation structure includes a dielectric stack including interleaved third dielectric layers and fourth dielectric layers. The third dielectric layers are in contact with the first dielectric layers, and the fourth dielectric layers are in contact with the first conductor layers.

Abstract: A method for manufacturing a self-aligned SiGe HBT device by nonselective epitaxy. An expected germanium concentration, an expected boron doping percent and an expected carbon concentration can be obtained within a wide range by low-temperature selective epitaxy of SiGe. However, due to the influences of different doping ratios on the selectivity of epitaxial growth, a desired impurity distribution can be obtained after repeated experiments when selective epitaxy is used for device research and development, thus, delaying the research and development progress. According to the method of the present disclosure, nonselective epitaxy is adopted in an extrinsic base region, so that a deposition layer can be monocrystalline or polycrystalline, process complexity is low, and device performance is good.

Abstract: A radio frequency LDMOS device, wherein the drift region includes a first injection region and a second injection region; the first injection region situated between a second lateral surface of a polysilicon gate and a second lateral surface of a first Faraday shielding layer; the second injection region situated between the second lateral surface of the first Faraday shielding layer and the drain region and encloses the drain region; the second lateral surface of the second Faraday shielding layer is a surface of a side near the drain region, the maximum electric field strength of the drift region on the bottom of the second lateral surface of the second Faraday shielding layer is regulated via regulation of the doping concentration of the second injection region; the doping concentration of the first injection region is higher than the second injection region.

Abstract: A radio frequency LDMOS device, wherein the drift region includes a first injection region and a second injection region; the first injection region situated between a second lateral surface of a polysilicon gate and a second lateral surface of a first Faraday shielding layer; the second injection region situated between the second lateral surface of the first Faraday shielding layer and the drain region and encloses the drain region; the second lateral surface of the second Faraday shielding layer is a surface of a side near the drain region, the maximum electric field strength of the drift region on the bottom of the second lateral surface of the second Faraday shielding layer is regulated via regulation of the doping concentration of the second injection region; the doping concentration of the first injection region is higher than the second injection region.

Abstract: A radio frequency (RF) laterally diffused metal oxide semiconductor (LDMOS) device is disclosed which additionally includes a lightly-doped P-type buried layer under a P-type channel region and a moderately-dope P-type buried layer in the lightly-doped P-type buried layer. The two buried layers result in a lower base resistance for an equivalent parasitic NPN transistor, thereby impeding the occurrence of snapback in the device. Additionally, an equivalent reverse-biased diode formed between the channel region and the buried layers is capable of clamping the drain-source voltage of the device and sinking redundant currents to a substrate thereof. Furthermore, the design of a gate oxide layer of the RF LDMOS device to have a greater thickness at a proximal end to a drain region can help to reduce the hot-carrier effect, and having a smaller thickness at a proximal end to the source region can improve the transconductance of the RF LDMOS device.

Abstract: A method of fabricating a P-type surface-channel laterally diffused metal oxide semiconductor device includes forming a gate structure with polysilicon and metal silicide, and the processes of channel implantation, long-time high-temperature drive-in, formation of a heavily doped N-type polysilicon sinker and boron doping of a polysilicon gate, are performed in this order, thereby ensuring the gate not to be doped with boron during its formation. The high-temperature drive-in process is allowed to be carried out to form a channel with a desired width, and a short channel effect which may cause penetration or electric leakage of the resulting device is prevented. As the polysilicon gate is not processed by any high-temperature drive-in process after it is doped with boron, the penetration of boron through a gate oxide layer and the diffusion of N-type impurity contained in the heavily doped polysilicon sinker into the channel or other regions are prevented.

Abstract: A radio frequency (RF) laterally diffused metal oxide semiconductor (LDMOS) device is disclosed which additionally includes a lightly-doped P-type buried layer under a P-type channel region and a moderately-dope P-type buried layer in the lightly-doped P-type buried layer. The two buried layers result in a lower base resistance for an equivalent parasitic NPN transistor, thereby impeding the occurrence of snapback in the device. Additionally, an equivalent reverse-biased diode formed between the channel region and the buried layers is capable of clamping the drain-source voltage of the device and sinking redundant currents to a substrate thereof. Furthermore, the design of a gate oxide layer of the RF LDMOS device to have a greater thickness at a proximal end to a drain region can help to reduce the hot-carrier effect, and having a smaller thickness at a proximal end to the source region can improve the transconductance of the RF LDMOS device.

Abstract: A method of fabricating a P-type surface-channel laterally diffused metal oxide semiconductor device includes forming a gate structure with polysilicon and metal silicide, and the processes of channel implantation, long-time high-temperature drive-in, formation of a heavily doped N-type polysilicon sinker and boron doping of a polysilicon gate, are performed in this order, thereby ensuring the gate not to be doped with boron during its formation. The high-temperature drive-in process is allowed to be carried out to form a channel with a desired width, and a short channel effect which may cause penetration or electric leakage of the resulting device is prevented. As the polysilicon gate is not processed by any high-temperature drive-in process after it is doped with boron, the penetration of boron through a gate oxide layer and the diffusion of N-type impurity contained in the heavily doped polysilicon sinker into the channel or other regions are prevented.

Abstract: A SiGe HBT formed on a silicon substrate is disclosed. An active area is isolated by field oxide regions; a collector region is formed in the active area and extends into the bottom of the field oxide regions; pseudo buried layers are formed at the bottom of the field oxide regions, wherein each pseudo buried layer is separated by a lateral distance from the active area and connected to a lateral extension part of the collector region; first deep hole contacts are formed on top of the pseudo buried layers in the field oxide regions to pick up collector electrodes; a plurality of second deep hole contacts with a floating structure, are formed in the field oxide region on top of a lateral extension part of the collector region, wherein N-type implantation regions are formed at the bottom of the second deep hole contacts.

Abstract: The present invention provides a multi-finger structure of a SiGe heterojunction bipolar transistor (HBT). It is consisted of plural SiGe HBT single cells. The multi-finger structure is in a form of C/BEBC/BEBC/.../C, wherein, C, B, E respectively stands for collector, base and emitter; CBEBC stands for a SiGe HBT single cell. The collector region is consisted of an n type ion implanted layer inside the active region. The bottom of the implanted layer is connected to two n type pseudo buried layers. The two pseudo buried layers are formed through implantation to the bottom of the shallow trenches that surround the collector active region. Two collectors are picked up by deep trench contact through the field oxide above the two pseudo buried layers. The present invention can reduce junction capacitance, decrease collector electrode output resistance, and improve device frequency characteristics.

Abstract: A SiGe HBT formed on a silicon substrate is disclosed. An active area is isolated by field oxide regions; a collector region is formed in the active area and extends into the bottom of the field oxide regions; pseudo buried layers are formed at the bottom of the field oxide regions, wherein each pseudo buried layer is separated by a lateral distance from the active area and connected to a lateral extension part of the collector region; first deep hole contacts are formed on top of the pseudo buried layers in the field oxide regions to pick up collector electrodes; a plurality of second deep hole contacts with a floating structure, are formed in the field oxide region on top of a lateral extension part of the collector region, wherein N-type implantation regions are formed at the bottom of the second deep hole contacts.

Abstract: A manufacturing method of a SiGe HBT is disclosed. Alter an emitter region is formed, an ion implantation is performed with a tilt angle to a base region by using an extrinsic base ion implantation process; boron ions are implanted during the extrinsic base ion implantation with an implantation dose from 1e15 to 1e16 cm?2, an implantation energy from 5 to 30 KeV, and a tilt angle from 5 to 30 degrees. The tilt angle enables the implantation of P-type impurities into the part of the intrinsic base region at the bottom of the emitter window dielectric layer as well as the extrinsic base region, so that the base region excluding the part of the intrinsic base region in contact with the emitter region is entirely doped with P-type impurities, thus reducing the base resistance and improving the frequency characteristic of a transistor without needing to reduce its size.

Abstract: The present invention provides a multi-finger structure of a SiGe heterojunction bipolar transistor (HBT). It is consisted of plural SiGe HBT single cells. The multi-finger structure is in a form of C/BEBC/BEBC/.../C, wherein, C, B, E respectively stands for collector, base and emitter; CBEBC stands for a SiGe HBT single cell. The collector region is consisted of an n type ion implanted layer inside the active region. The bottom of the implanted layer is connected to two n type pseudo buried layers. The two pseudo buried layers are formed through implantation to the bottom of the shallow trenches that surround the collector active region. Two collectors are picked up by deep trench contact through the field oxide above the two pseudo buried layers. The present invention can reduce junction capacitance, decrease collector electrode output resistance, and improve device frequency characteristics.