Abstract: Systems, apparatuses and methods may provide for technology that initializes an integrated memory of a processor during a boot sequence and conducts a runtime initialization of an external system memory associated with the processor. The technology may also bypass the runtime initialization of the external system memory during the boot sequence.

Abstract: A reference voltage value and a chip select (CS) signal timing delay provided to memory devices can be determined based on samples of the CS signal received by the memory devices. The CS signal can be provided to the memory devices with varying time delays and for various reference voltages. Various samples of the CS signal from the memory devices can indicate different times for rising and falling edges of the CS signal. A composite signal eye can be generated by the latest occurring rising edge and the earliest occurring falling edge of the CS signal. The reference voltage value and timing delay can be chosen based on the composite signal eye width that is the closest to a reference eye width.

Abstract: Systems, apparatuses and methods may provide for technology that handles failures in memory hardware (e.g., dynamic random access memory (DRAM)) via runtime post package repair. Such technology may include operations to perform a runtime post package repair in response to a memory hardware failure detected in the memory. In such an example, the runtime post package repair may be done after power up boot operations have been completed.

Abstract: A host controller apparatus for determining information related to a time shift for transmitting instructions on a command and address bus includes an interface for transmitting a plurality of instruction signals to a memory module via the command and address bus and for receiving a loopback feedback signal from the memory module. The host controller apparatus further includes a control module configured to transmit the plurality of instruction signals to the memory module via the command and address bus. The control module is configured to receive the loopback feedback signal from the memory module. The loopback feedback signal includes a looped-back composite version of the plurality of instruction signals. The control module is configured to determine the information related to the time shift for transmitting instructions on the command and address bus based on the loopback feedback signal.

Abstract: A host controller apparatus for determining information related to a time shift for transmitting instructions on a command and address bus includes an interface for transmitting a plurality of instruction signals to a memory module via the command and address bus and for receiving a loopback feedback signal from the memory module. The host controller apparatus further includes a control module configured to transmit the plurality of instruction signals to the memory module via the command and address bus. The control module is configured to receive the loopback feedback signal from the memory module. The loopback feedback signal includes a looped-back composite version of the plurality of instruction signals. The control module is configured to determine the information related to the time shift for transmitting instructions on the command and address bus based on the loopback feedback signal.