Abstract: The present teaching relates to method and system for charging a rechargeable battery deployed in an electric apparatus. The system resides in the electric apparatus. The system comprises a motor, an inverter, an output rectifier, a configurator, and a controller. The motor comprises a stator having a plurality of stator teeth and a plurality of stator windings wounded on the plurality of stator teeth. The inverter comprises a plurality of power switch devices. The configurator comprises a plurality of contactors coupled with the plurality of stator windings and the plurality of power switch devices. The controller controls the plurality of power switch devices and the plurality of contactors, so as to configure the system to operate in one of a traction mode and a charging mode.

Abstract: At an electronic device that is coupled to a set of circuits configured to supply electricity to respective on-board charging systems of one or more electric vehicles: detecting activation of a first electric vehicle charging connection; in response to detecting the activation of the first electric vehicle charging connection, obtaining a first communication signal through the first electric vehicle charging connection; decoding the first communication signal to extract a respective vehicle identifier corresponding to an on-board charging system of a first electric vehicle that is connected to the set of circuits through the first electric charging connection; configuring a first charging mode for the on-board charging system of the first electric vehicle in accordance with the respective vehicle identifier; and enabling charging of the first electric vehicle through the first electric vehicle charging connection in accordance with the first charging mode.

Abstract: At an electronic device that is coupled to a main input of an electricity demand center on an electric grid: activating load monitoring for the electricity demand center; determining an electricity consumption cap for a current electricity consumption cycle at the electricity demand center; during the current electricity consumption cycle, detecting activation of a first electric vehicle charging connection; and in response to detecting activation of the first electric vehicle charging connection, enforcing an output power cap for EV-charging circuits at the electricity demand center, including dynamically adjusting a current output power of the first electric vehicle charging connection in accordance with a difference between the electricity consumption cap for the current electricity consumption cycle and a current load on non-EV charging circuits at the electricity demand center.

Abstract: At an electronic device that is coupled to a main input of an electricity demand center on an electric grid: activating load monitoring for the electricity demand center; determining an electricity consumption cap for a current electricity consumption cycle at the electricity demand center; during the current electricity consumption cycle, detecting activation of a first electric vehicle charging connection; and in response to detecting activation of the first electric vehicle charging connection, enforcing an output power cap for EV-charging circuits at the electricity demand center, including dynamically adjusting a current output power of the first electric vehicle charging connection in accordance with a difference between the electricity consumption cap for the current electricity consumption cycle and a current load on non-EV charging circuits at the electricity demand center.

Abstract: At an electronic device that is coupled to a set of circuits configured to supply electricity to respective on-board charging systems of one or more electric vehicles: detecting activation of a first electric vehicle charging connection; in response to detecting the activation of the first electric vehicle charging connection, obtaining a first communication signal through the first electric vehicle charging connection; decoding the first communication signal to extract a respective vehicle identifier corresponding to an on-board charging system of a first electric vehicle that is connected to the set of circuits through the first electric charging connection; configuring a first charging mode for the on-board charging system of the first electric vehicle in accordance with the respective vehicle identifier; and enabling charging of the first electric vehicle through the first electric vehicle charging connection in accordance with the first charging mode.

Abstract: In an electric vehicle charging and traction system with an inverter configured to be coupled to at most one DC power source and provide AC power, a first motor coupled to the inverter, a second motor coupled to the first motor, a converter coupled to the second motor and to a rechargeable DC power unit, and a switching mechanism configured to control coupling or decoupling of the inverter: in charging mode, decouple the inverter from the rechargeable DC power unit, couple the inverter to a second DC power source, and run the first motor at speed in a first direction and the second motor with negative torque to generate current; and in traction mode, decouple the inverter from the second DC power source, couple the inverter to the rechargeable DC power unit, and run the first and second motors with nonzero torque in a same torque direction.

Abstract: An electric vehicle charging and traction system includes an inverter with an input terminal configured to receive DC power and an output terminal configured to provide AC power, a first motor coupled to the output terminal of the inverter, a second motor coupled to the first motor, a converter with AC terminals coupled to the second motor and positive and negative DC terminals coupled to a rechargeable DC power unit, and a switching mechanism configured to control coupling or decoupling of the input terminal of the inverter with at most one of a plurality of DC power sources.

Abstract: A selective semiconductor deposition process that employs an alternating sequence of a deposition step and an etch step. During each deposition step, a semiconductor material is deposited on single crystalline surfaces at a greater deposition rate than on insulator surfaces. A combination of hydrogen chloride and a germanium-containing gas is employed within each etch step. The germanium-containing gas is employed to enhance the etch rate of hydrogen chloride, thereby enabling an effective etch process at temperatures as low as 380° C. Deposited semiconductor material is removed from above insulator surfaces, while a fraction of the deposited semiconductor material remains on semiconductor surfaces after each etch step, thereby providing a selective deposition of the semiconductor material.

Abstract: Carbon-doped semiconductor material portions are formed on a subset of surfaces of underlying semiconductor surfaces contiguously connected to a channel of a field effect transistor. Carbon-doped semiconductor material portions can be formed by selective epitaxy of a carbon-containing semiconductor material layer or by shallow implantation of carbon atoms into surface portions of the underlying semiconductor surfaces. The carbon-doped semiconductor material portions can be deposited as layers and subsequently patterned by etching, or can be formed after formation of disposable masking spacers. Raised source and drain regions are formed on the carbon-doped semiconductor material portions and on physically exposed surfaces of the underlying semiconductor surfaces.

Abstract: Carbon-doped semiconductor material portions are formed on a subset of surfaces of underlying semiconductor surfaces contiguously connected to a channel of a field effect transistor. Carbon-doped semiconductor material portions can be formed by selective epitaxy of a carbon-containing semiconductor material layer or by shallow implantation of carbon atoms into surface portions of the underlying semiconductor surfaces. The carbon-doped semiconductor material portions can be deposited as layers and subsequently patterned by etching, or can be formed after formation of disposable masking spacers. Raised source and drain regions are formed on the carbon-doped semiconductor material portions and on physically exposed surfaces of the underlying semiconductor surfaces.

Abstract: Carbon-doped semiconductor material portions are formed on a subset of surfaces of underlying semiconductor surfaces contiguously connected to a channel of a field effect transistor. Carbon-doped semiconductor material portions can be formed by selective epitaxy of a carbon-containing semiconductor material layer or by shallow implantation of carbon atoms into surface portions of the underlying semiconductor surfaces. The carbon-doped semiconductor material portions can be deposited as layers and subsequently patterned by etching, or can be formed after formation of disposable masking spacers. Raised source and drain regions are formed on the carbon-doped semiconductor material portions and on physically exposed surfaces of the underlying semiconductor surfaces.

Abstract: Carbon-doped semiconductor material portions are formed on a subset of surfaces of underlying semiconductor surfaces contiguously connected to a channel of a field effect transistor. Carbon-doped semiconductor material portions can be formed by selective epitaxy of a carbon-containing semiconductor material layer or by shallow implantation of carbon atoms into surface portions of the underlying semiconductor surfaces. The carbon-doped semiconductor material portions can be deposited as layers and subsequently patterned by etching, or can be formed after formation of disposable masking spacers. Raised source and drain regions are formed on the carbon-doped semiconductor material portions and on physically exposed surfaces of the underlying semiconductor surfaces.

Abstract: Carbon-doped semiconductor material portions are formed on a subset of surfaces of underlying semiconductor surfaces contiguously connected to a channel of a field effect transistor. Carbon-doped semiconductor material portions can be formed by selective epitaxy of a carbon-containing semiconductor material layer or by shallow implantation of carbon atoms into surface portions of the underlying semiconductor surfaces. The carbon-doped semiconductor material portions can be deposited as layers and subsequently patterned by etching, or can be formed after formation of disposable masking spacers. Raised source and drain regions are formed on the carbon-doped semiconductor material portions and on physically exposed surfaces of the underlying semiconductor surfaces.

Abstract: A method of making a semiconductor device patterns a first fin in a pFET region, and patterns a second fin in an nFET region. A plurality of conformal microlayers containing a straining material are deposited on the first and second fins. A protective cap material is formed on the first fin, and the conformal layers are selectively removed from the second fin. The straining material is then thermally diffused into the first fin. The protective cap material is removed from the first fin after the thermal annealing and after the conformal micro layers are selectively removed from the second fin.

Abstract: Carbon-doped semiconductor material portions are formed on a subset of surfaces of underlying semiconductor surfaces contiguously connected to a channel of a field effect transistor. Carbon-doped semiconductor material portions can be formed by selective epitaxy of a carbon-containing semiconductor material layer or by shallow implantation of carbon atoms into surface portions of the underlying semiconductor surfaces. The carbon-doped semiconductor material portions can be deposited as layers and subsequently patterned by etching, or can be formed after formation of disposable masking spacers. Raised source and drain regions are formed on the carbon-doped semiconductor material portions and on physically exposed surfaces of the underlying semiconductor surfaces.

Abstract: Semiconductor substrate with a deformed gate region and a method for the fabrication thereof. The semiconductor substrate has improved device performance compared to devices without a deformed gate region and decreased dopant loss compared to devices with deformed source/drain regions.

Abstract: Semiconductor structures are disclosed that include at least one FET gate stack located on a semiconductor substrate. The at least one FET gate stack includes source and drain extension regions located within the semiconductor substrate. A device channel is also present between the source and drain extension regions and beneath the at least one gate stack. Embedded stressor elements are located on opposite sides of the at least one FET gate stack and within the semiconductor substrate. Each stressor element includes a lower layer of a first epitaxy doped semiconductor material having a lattice constant that is different from a lattice constant of the semiconductor substrate and imparts a strain in the device channel, and an upper layer of a second epitaxy doped semiconductor material. At least one monolayer of dopant is located within the upper layer of each of the embedded stressor elements.

Abstract: A method of making a semiconductor device patterns a first fin in a pFET region, and patterns a second fin in an nFET region. A plurality of conformal microlayers containing a straining material are deposited on the first and second fins. A protective cap material is formed on the first fin, and the conformal layers are selectively removed from the second fin. The straining material is then thermally diffused into the first fin. The protective cap material is removed from the first fin after the thermal annealing and after the conformal micro layers are selectively removed from the second fin.

Abstract: A semiconductor substrate having transistor structures and test structures with spacing between the transistor structures smaller than the spacing between the test structures is provided. A first iteratively performed deposition and etch process includes: depositing a first doped epitaxial layer having a first concentration of a dopant over the semiconductor substrate, and etching the first doped epitaxial layer. A second iteratively performed deposition and etch process includes: depositing a second doped epitaxial layer having a second concentration of the dopant higher than the first concentration over the semiconductor substrate, and etching the second doped epitaxial layer. The first concentration results in a first net growth rate over the transistor structures and the second concentration results in a lower, second net growth rate over the test structures than the transistor structures, resulting in reduced pattern loading.

Abstract: A semiconductor substrate having transistor structures and test structures with spacing between the transistor structures smaller than the spacing between the test structures is provided. A first iteratively performed deposition and etch process includes: depositing a first doped epitaxial layer having a first concentration of a dopant over the semiconductor substrate, and etching the first doped epitaxial layer. A second iteratively performed deposition and etch process includes: depositing a second doped epitaxial layer having a second concentration of the dopant higher than the first concentration over the semiconductor substrate, and etching the second doped epitaxial layer. The first concentration results in a first net growth rate over the transistor structures and the second concentration results in a lower, second net growth rate over the test structures than the transistor structures, resulting in reduced pattern loading.