Patents by Inventor Zhengqing SUN

Zhengqing SUN has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11914344
    Abstract: Embodiments of the present disclosure provide a control method and apparatus for hybrid process recipes, and a device and a medium. The control method includes: acquiring hybrid process recipe operation groups associated with process recipes operated by etching chambers of an etching machine, where different process recipes correspond to different hybrid process recipe operation groups; acquiring a switching rule of different hybrid process recipe operation groups; and controlling, based on a reserved process recipe for a real-time reserved demand of a target etching chamber and a requirement of the switching rule, the etching machine to automatically switch to a target hybrid process recipe operation group associated with the reserved process recipe.
    Type: Grant
    Filed: April 11, 2022
    Date of Patent: February 27, 2024
    Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventors: Xingle Zhao, Yuming Wang, Zhengqing Sun
  • Publication number: 20230048193
    Abstract: The invention provides a semiconductor structure and a fabrication method for same. The semiconductor structure comprises: a substrate; a plurality of word-line structures extending along a first direction on the substrate and arranged at intervals along a second direction, wherein the second direction is perpendicular to the first direction; a plurality of spacer structures disposed above the plurality of word-line structures, wherein at least one of the plurality of spacer structures comprises a first spacer layer and an air gap, the first spacer layer is disposed at a bottom portion of the spacer structures, the air gap is disposed on the first spacer layer, and the air gap is located between the plurality of first spacer layers along the second direction; and a plurality of contact plugs disposed between the plurality of spacer structures.
    Type: Application
    Filed: June 28, 2022
    Publication date: February 16, 2023
    Inventors: Ming CHENG, Ran LI, Zhengqing SUN, Xing JIN
  • Publication number: 20230050040
    Abstract: Embodiments of the present disclosure provide a control method and apparatus for hybrid process recipes, and a device and a medium. The control method includes: acquiring hybrid process recipe operation groups associated with process recipes operated by etching chambers of an etching machine, where different process recipes correspond to different hybrid process recipe operation groups; acquiring a switching rule of different hybrid process recipe operation groups; and controlling, based on a reserved process recipe for a real-time reserved demand of a target etching chamber and a requirement of the switching rule, the etching machine to automatically switch to a target hybrid process recipe operation group associated with the reserved process recipe.
    Type: Application
    Filed: April 11, 2022
    Publication date: February 16, 2023
    Inventors: Xingle Zhao, Yuming Wang, Zhengqing Sun
  • Publication number: 20220157827
    Abstract: A manufacturing method for a semiconductor structure includes: a semiconductor substrate is provided, the semiconductor substrate includes multiple first regions and second regions which are alternately disposed; multiple bitline structures are formed on the semiconductor substrate, any one of the bitline structures penetrates through the first regions and the second regions; the bitline structures in the first regions are etched, to enable each sidewall on two sides of each of the bitline structure to be in a step shape; and multiple electrode structures are formed, any one of the electrode structures includes a conductive plug and a contact pad in mutually electric connection, and each conductive plug is disposed at a respective first region, disposed between two neighboring bitline structures and connected to the semiconductor substrate.
    Type: Application
    Filed: January 27, 2022
    Publication date: May 19, 2022
    Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventors: Xing JIN, Zhengqing SUN, Ming CHENG, Ran LI
  • Publication number: 20220115385
    Abstract: The disclosure relates to a method for manufacturing a semiconductor device, a semiconductor device and a memory, and belongs to the field of semiconductor technologies. The method for manufacturing the semiconductor device includes: a semiconductor substrate is provided; a shallow trench isolation structure and a plurality of grooves arranged at intervals are formed on the semiconductor substrate, and a substrate bulge is formed between two adjacent grooves; a gate oxide layer is deposited on the surface of the semiconductor substrate, and the gate oxide layer covers the grooves and the substrate bulge; a gate structure is formed on the gate oxide layer, the gate structure includes a first gate structure and a second gate structure, and the first gate structure covers the surface of the substrate bulge; and a source electrode and a drain electrode are formed in the semiconductor substrate.
    Type: Application
    Filed: September 8, 2021
    Publication date: April 14, 2022
    Inventors: Shiran ZHANG, Zhengqing SUN, Youquan YU
  • Publication number: 20220093604
    Abstract: A semiconductor structure manufacturing method includes: providing a substrate; forming a first insulating layer covering the substrate, and patterning the first insulating layer to form a plurality of vias and a plurality of isolation structures that are alternatingly distributed; forming conductive contact plugs in the vias respectively, where the conductive contact plugs cover bottoms of the vias and each includes a first region and a second region adjacent to each other, and the conductive contact plugs located in the first regions cover outer walls of the isolation structures and extend along the outer walls to surfaces of the isolation structures distal from the substrate; and forming a passivation layer covering side walls and surfaces of the conductive contact plugs.
    Type: Application
    Filed: September 9, 2021
    Publication date: March 24, 2022
    Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventors: Zhengqing SUN, Xing JIN