Abstract: The present disclosure provides a semiconductor structure and a method for forming the semiconductor structure. The method includes: providing a substrate including a device region and a guard ring region surrounding the device region; and forming a power device in the device region and forming a guard ring in the guard ring region, wherein the guard ring is doped with a first dopant ion that is formed by a partial doping process used in a formation of the power device, and a conductivity type of the first dopant ion in the guard ring is different from a device type of the power device. Since the guard ring is formed by the necessary doping process used in forming the power device, additional photomask process and doping process for forming the guard ring is omitted, effectively reducing process steps and process costs.

Abstract: A method for manufacturing an IGBT device includes: forming a source of the IGBT device in a substrate, wherein the substrate is an MCZ substrate; performing annealing processing on the substrate, wherein a layer of oxide is formed on the surface of the source during an annealing process; forming an interlayer dielectric layer on the substrate, wherein the interlayer dielectric layer is comprised of a silicon nitride layer, a first type oxide layer, and a second type oxide layer, and a material used to form the first type oxide layer is different from a material used to form the second type oxide layer; and performing nitrogen annealing processing on the substrate.

Abstract: A method for manufacturing an IGBT device includes: forming a source of the IGBT device in a substrate, wherein the substrate is an MCZ substrate; performing annealing processing on the substrate, wherein a layer of oxide is formed on the surface of the source during an annealing process; forming an interlayer dielectric layer on the substrate, wherein the interlayer dielectric layer is comprised of a silicon nitride layer, a first type oxide layer, and a second type oxide layer, and a material used to form the first type oxide layer is different from a material used to form the second type oxide layer; and performing nitrogen annealing processing on the substrate.

Abstract: The present application relates to the field of semiconductor forming technologies, in particular to an interlayer dielectric layer structure for a power MOS device and a method for making the same. The interlayer dielectric layer structure for a power MOS device comprises a silicon-rich oxide SiOx film layer deposited on the surface of the power MOS device, wherein a silicon dioxide film layer is deposited on the silicon-rich oxide SiOx film layer. The method for forming an interlayer dielectric layer structure for a power MOS device comprises the following steps: depositing a silicon-rich oxide SiOx film layer on the surface of the power MOS device; and depositing a silicon dioxide film layer on the silicon-rich oxide SiOx film layer.

Abstract: A manufacturing method for a shielded gate trench device comprises the following steps: Step 1, forming a gate trench in a first epitaxial layer; Step 2, forming a first dielectric layer and fully filling the gate trench with a first polysilicon layer; Step 3, forming a top trench: Step 31, carrying out primary polysilicon dry-etching; Step 32, carrying out primary dielectric layer wet-etching to decrease the thickness of the first dielectric layer in the top trench; Step 33, carrying out secondary polysilicon dry-etching; Step 34, carrying out secondary dielectric layer wet-etching to remove the rest of the first dielectric layer on a side face of the top trench and to form the top trench; and Step 4, forming a trench gate in the top trench. By adoption of the manufacturing method, the gate-source capacitance and the gate-drain capacitance can be decreased, and thus, the input capacitance is decreased.

Abstract: A manufacturing method for a shielded gate trench device comprises the following steps: Step 1, forming a gate trench in a first epitaxial layer; Step 2, forming a first dielectric layer and fully filling the gate trench with a first polysilicon layer; Step 3, forming a top trench: Step 31, carrying out primary polysilicon dry-etching; Step 32, carrying out primary dielectric layer wet-etching to decrease the thickness of the first dielectric layer in the top trench; Step 33, carrying out secondary polysilicon dry-etching; Step 34, carrying out secondary dielectric layer wet-etching to remove the rest of the first dielectric layer on a side face of the top trench and to form the top trench; and Step 4, forming a trench gate in the top trench. By adoption of the manufacturing method, the gate-source capacitance and the gate-drain capacitance can be decreased, and thus, the input capacitance is decreased.

Abstract: A sensitive information processing method, device and server, and a security determination system. The method includes acquiring to-be-processed information in a page; determining whether the to-be-processed information is sensitive information according to a preset sensitive information identification strategy; performing processing according to a preset sensitive information processing strategy when the to-be-processed information is sensitive information, to form processed sensitive information; and substituting the corresponding to-be-processed information in the page with the processed sensitive information, to form a page with the processed sensitive information. By using the example embodiments of the present application, identification and processing for sensitive information in a page returned to a user may be completed on a server terminal, which improves the security of the sensitive information in the page.

Abstract: A sensitive information processing method, device and server, and a security determination system. The method includes acquiring to-be-processed information in a page; determining whether the to-be-processed information is sensitive information according to a preset sensitive information identification strategy; performing processing according to a preset sensitive information processing strategy when the to-be-processed information is sensitive information, to form processed sensitive information; and substituting the corresponding to-be-processed information in the page with the processed sensitive information, to form a page with the processed sensitive information. By using the example embodiments of the present application, identification and processing for sensitive information in a page returned to a user may be completed on a server terminal, which improves the security of the sensitive information in the page.

Abstract: A stack semiconductor package structure includes a substrate; a second chip comprising a plurality of conductive bumps formed on a surface thereof; and a first chip positioned on the second chip, wherein the second chip is electrically connected to the substrate through the plurality of conductive bumps in a flip-chip manner, and wherein the first chip is electrically connected to the second chip through a plurality of bonding wires.