Patents by Inventor Zhengsheng Han

Zhengsheng Han has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10176287
    Abstract: The invention discloses an STI stress effect modeling method and device of an MOS device, and belongs to the technical field of parameter extraction modeling of devices. The method comprises the following steps: introducing the influence of temperature parameters on the STI stress effect of the MOS device, so as to form a function showing that the STI stress effect of the MOS device changes along with the temperature parameters; extracting the model parameter Model1 of the MOS device at normal temperature; on the basis of the Model1, extracting the parameter Model2 that the STI stress affects the properties of the MOS device at normal temperature; and on the basis of the Model2, extracting fitting parameters of the MOS device in the function so as to acquire final model parameters. The device comprises a first module, a second module, a third module and a fourth module.
    Type: Grant
    Filed: April 25, 2014
    Date of Patent: January 8, 2019
    Assignee: The Institute of Microelectronics of Chinese Academy of Science
    Inventors: Jianhui Bu, Shuzhen Li, Jiajun Luo, Zhengsheng Han
  • Patent number: 9626467
    Abstract: The present invention provides a SOI MOS device modeling method. The SOI MOS device is one having a source-drain injection not reaching the bottom. The method comprises: a) establishing an overall model comprising a primary MOS device model simulating an SOI MOS device having the source-drain injection reaching the bottom, a source body PN junction bottom capacitance model simulating a source body PN junction bottom capacitance, and a drain body PN junction bottom capacitance model simulating a drain body PN junction bottom capacitance; and b) extracting parameters respectively for the primary MOS device model, the source body PN junction bottom capacitance model, and the drain body PN junction bottom capacitance model in the overall model. In the prior art, the source body junction bottom capacitance and the drain body junction bottom capacitance in the SOI MOS device having a source-drain injection not reaching the bottom affect the performances of the device.
    Type: Grant
    Filed: September 21, 2012
    Date of Patent: April 18, 2017
    Assignee: Institute of Microelectronics, Chinese Academy of Sciences
    Inventors: Jianhui Bu, Jinshun Bi, Jiajun Luo, Zhengsheng Han
  • Patent number: 9536585
    Abstract: The present invention provides an improved SRAM memory cell based on a DICE structure, which comprises following structures: four inverter structures formed through arranging PMOS transistors and NMOS transistors in series, wherein the part between the drains of a PMOS transistor and an NMOS transistor serves as a storage node; each storage node controls the gate voltage of an NMOS transistor of the other inverter structure and of a PMOS transistor of another inverter structure; a transmission structure consisting of four NMOS transistors, whose source, gate and drain are respectively connected with a bit line/bit bar line, a word line and a storage node.
    Type: Grant
    Filed: May 28, 2014
    Date of Patent: January 3, 2017
    Assignee: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES
    Inventors: Mengxin Liu, Xin Liu, Fazhan Zhao, Zhengsheng Han
  • Publication number: 20160259876
    Abstract: The invention discloses an STI stress effect modeling method and device of an MOS device, and belongs to the technical field of parameter extraction modeling of devices. The method comprises the following steps: introducing the influence of temperature parameters on the STI stress effect of the MOS device, so as to form a function showing that the STI stress effect of the MOS device changes along with the temperature parameters; extracting the model parameter Model1 of the MOS device at normal temperature; on the basis of the Model1, extracting the parameter Model2 that the STI stress affects the properties of the MOS device at normal temperature; and on the basis of the Model2, extracting fitting parameters of the MOS device in the function so as to acquire final model parameters. The device comprises a first module, a second module, a third module and a fourth module.
    Type: Application
    Filed: April 25, 2014
    Publication date: September 8, 2016
    Inventors: Jianhui Bu, Shuzhen Li, Jiajun Luo, Zhengsheng Han
  • Publication number: 20160260474
    Abstract: The present invention provides an improved SRAM memory cell based on a DICE structure, which comprises following structures: four inverter structures formed through arranging PMOS transistors and NMOS transistors in series, wherein the part between the drains of a PMOS transistor and an NMOS transistor serves as a storage node; each storage node controls the gate voltage of an NMOS transistor of the other inverter structure and of a PMOS transistor of another inverter structure; a transmission structure consisting of four NMOS transistors, whose source, gate and drain are respectively connected with a bit line/bit bar line, a word line and a storage node.
    Type: Application
    Filed: May 28, 2014
    Publication date: September 8, 2016
    Inventors: Mengxin Liu, Xin Liu, Fazhan Zhao, Zhengsheng Han
  • Patent number: 9111995
    Abstract: A method for improving anti-radiation performance of SOI structure that includes implementing particle implantations of high-energy neutrons, protons and ?-rays to a buried oxide layer of an SOI structure, and then performing annealing process. The high-energy particle implantation introduces displacement damage to the buried oxide layer of the SOI structure.
    Type: Grant
    Filed: October 25, 2012
    Date of Patent: August 18, 2015
    Assignee: Institute of Microelectronics, Chinese Academy of Sciences
    Inventors: Yinxue Lv, Jinshun Bi, Jiajun Luo, Zhengsheng Han, Tianchun Ye
  • Publication number: 20150177312
    Abstract: The present invention provides a method for determining PN junction depth comprising: a) measuring a square resistance in a well region; b) forming a junction type field effect transistor in the well region, changing a gate electrode voltage and measuring a source-drain resistance; c) calculating the PN junction depth according to the measured square resistance, source-drain resistance and related process parameters of the junction type field effect transistor. As compared with the prior art, the technical solution in this invention determines the PN junction depth by electrical measurement, is thus simple and feasible, and has better repeatability.
    Type: Application
    Filed: September 21, 2012
    Publication date: June 25, 2015
    Inventors: Jianhui Bu, Jinshun Bi, Jiajun Luo, Zhengsheng Han
  • Publication number: 20150178429
    Abstract: The present invention provides a SOI MOS device modeling method. The SOI MOS device is one having a source-drain injection not reaching the bottom. The method comprises: a) establishing an overall model comprising a primary MOS device model simulating an SOI MOS device having the source-drain injection reaching the bottom, a source body PN junction bottom capacitance model simulating a source body PN junction bottom capacitance, and a drain body PN junction bottom capacitance model simulating a drain body PN junction bottom capacitance; and b) extracting parameters respectively for the primary MOS device model, the source body PN junction bottom capacitance model, and the drain body PN junction bottom capacitance model in the overall model. In the prior art, the source body junction bottom capacitance and the drain body junction bottom capacitance in the SOI MOS device having a source-drain injection not reaching the bottom affect the performances of the device.
    Type: Application
    Filed: September 21, 2012
    Publication date: June 25, 2015
    Inventors: Jianhui Bu, Jinshun Bi, Jiajun Luo, Zhengsheng Han
  • Publication number: 20150170915
    Abstract: The present invention provides a method for manufacturing a semiconductor structure, which is characterized in comprising following steps: providing an SOI substrate for forming a semiconductor structure; the SOI substrate comprises a monocrystalline silicon top layer, a buried oxide layer and a support substrate; and forming an amorphous region outside the area for forming a channel region of the semiconductor structure in the monocrystalline silicon top layer. The method provided by the present invention can effectively improve reliability of a gate dielectric layer formed on the SOI substrate.
    Type: Application
    Filed: September 21, 2012
    Publication date: June 18, 2015
    Applicant: Institute of Microelectroncis, Chinese Academy of Science
    Inventors: Jinshun Bi, Jiajun Luo, Zhengsheng Han
  • Patent number: 9032270
    Abstract: The present disclosure provides a device and method for storing encoded and/or decoded codes by re-using an encoder. The device and method for storing the encoded and/or decoded codes according to the present disclosure enables re-use of the encoder during a decoding process, which makes it unnecessary to use additional hardware and thereby reduces an area consumed by an EDAC (error detection and correction) decoder.
    Type: Grant
    Filed: September 21, 2011
    Date of Patent: May 12, 2015
    Assignee: Institute of Microelectronics, Chinese Academy of Sciences
    Inventors: Yiqi Wang, Zhengsheng Han
  • Publication number: 20140349463
    Abstract: The present invention provides a method for improving anti-radiation performance of SOI structure comprising following steps: implementing particle implantations of high-energy neutrons, protons and ?-rays to an SOI structure, and then performing annealing process. The present invention aims to improving anti-radiation performance of SOI devices by means of introducing displacement damage into a buried oxide layer through implantation of high-energy particles.
    Type: Application
    Filed: October 25, 2012
    Publication date: November 27, 2014
    Inventors: Yinxue Lv, Jinshun Bi, Jiajun Luo, Zhengsheng Han, Tianchun Ye
  • Publication number: 20140239385
    Abstract: A Field Effect Transistor (FET) and a method of manufacturing the same are provided. The FET may include a substrate; a source and a drain, one of which is formed on a bulge formed on a top surface of the substrate, and the other of which is formed in the substrate below but laterally offset from the bulge; a gate formed at a position where the bulge and the top surface of the substrate join each other; and a gate dielectric layer formed between the gate and the bulge and also between the gate and the top surface of the substrate. The FET has a vertical configuration, where the source is disposed on top of the bulge while the drain is disposed in the substrate, that is, the source and the drain are not in one same plane. As a result, the FET may have its area significantly reduced. Therefore, it is possible to improve an integration density of an IC and thus reduce cost.
    Type: Application
    Filed: September 21, 2012
    Publication date: August 28, 2014
    Applicant: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES
    Inventors: Jinshun Bi, Chaohe Hai, Zhengsheng Han, Jiajun Luo
  • Publication number: 20130346828
    Abstract: The present disclosure provides a device and method for storing encoded and/or decoded codes by re-using an encoder. The device and method for storing the encoded and/or decoded codes according to the present disclosure enables re-use of the encoder during a decoding process, which makes it unnecessary to use additional hardware and thereby reduces an area consumed by an EDAC (error detection and correction) decoder.
    Type: Application
    Filed: September 21, 2011
    Publication date: December 26, 2013
    Inventors: Yiqi Wang, Zhengsheng Han