Patents by Inventor Zhengtao Yu
Zhengtao Yu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11853680Abstract: The present disclosure relates to a chip design layout process. More specifically, the present disclosure is directed to an incremental routing-based pin assignment technique. One example method generally includes: performing routing and pin assignment for a chip design layout, one or more objects of the chip design layout being associated with a routing engine and a pin assignment engine stored in memory; detecting a change associated with the one or more objects of the chip design layout; updating, via one or more processors, at least one of the routing engine or the pin assignment engine stored in the memory in response to the detected change and based on the association between the one or more objects and the routing engine or pin assignment engine; and performing another routing and pin assignment based on the updated at least one of the routing engine or the pin assignment engine.Type: GrantFiled: July 2, 2021Date of Patent: December 26, 2023Assignee: Synopsys, Inc.Inventor: Zhengtao Yu
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Patent number: 11804074Abstract: The present disclosure relates to a method for recognizing facial expressions based on adversarial elimination. First, a facial expression recognition network is built based on a deep convolutional neural network. On a natural facial expression data set, the facial expression recognition network is trained through a loss function to make facial expression features easier to distinguish. Then some key features of input images are actively eliminated by using an improved confrontation elimination method to generate a new data set to train new networks with different weight distributions and feature extraction capabilities, forcing the network to perform expression classification discrimination based on more features, which reduces the influence of interference factors such as occlusion on the network recognition accuracy rate, and improving the robustness of the facial expression recognition network.Type: GrantFiled: September 27, 2021Date of Patent: October 31, 2023Assignees: Chongqing University, University of Electronic Science and Technology of China, Dibi (Chongqing) Intelligent Technology Research Institute Co., Ltd., Star Institute of Intelligent SystemsInventors: Yongduan Song, Feng Yang, Rui Li, Yiwen Zhang, Haoyuan Zhong, Jian Zhang, Shengtao Pan, Siyu Li, Zhengtao Yu
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Patent number: 11694016Abstract: A method includes receiving a netlist for a chip including a bus and determining, by one or more processors and based on the netlist, a first routing topology for the bus and through a routing region of the chip by comparing a demand of the bus to a capacity of a plurality of cells of the routing region. The method also includes generating a layout for the chip based on the first routing topology.Type: GrantFiled: June 11, 2021Date of Patent: July 4, 2023Assignee: Synopsys, Inc.Inventors: Zhengtao Yu, Balkrishna Rashingkar, David Peart, Douglas Chang, Yiding Han
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Publication number: 20220351043Abstract: The present disclosure discloses an adaptive high-precision compression method and system based on a convolutional neural network model, and belongs to the fields of artificial intelligence, computer vision, and image processing. According to the method of the present disclosure, coarse-grained pruning is performed on a neural network model by using a differential evolution algorithm first, and the coarse-grained space is quickly searched through an entropy importance criterion and an objective function with good guidance to obtain a near-optimal neural network structure. Then fine-grained search space is built on the basis of an optimal individual obtained from the coarse-grained search, and fine-grained pruning is performed on the neural network model by a differential evolution algorithm to obtain a network model with an optimal structure. Finally, the performance of the optimal model is restored by using a multi-teacher multi-step knowledge distillation network to reach the precision of an original model.Type: ApplicationFiled: September 27, 2021Publication date: November 3, 2022Applicants: Chongqing University, University of Electronic Science and Technology of China, Dibi (Chongqing) Intelligent Technology Research Institute Co., Ltd., Star Institute of Intelligent SystemsInventors: Yongduan Song, Feng Yang, Rui Li, Shengtao Pan, Siyu Li, Yiwen Zhang, Jian Zhang, Zhengtao Yu, Shichun Wang
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Publication number: 20220327308Abstract: The present disclosure relates to a method for recognizing facial expressions based on adversarial elimination. First, a facial expression recognition network is built based on a deep convolutional neural network. On a natural facial expression data set, the facial expression recognition network is trained through a loss function to make facial expression features easier to distinguish. Then some key features of input images are actively eliminated by using an improved confrontation elimination method to generate a new data set to train new networks with different weight distributions and feature extraction capabilities, forcing the network to perform expression classification discrimination based on more features, which reduces the influence of interference factors such as occlusion on the network recognition accuracy rate, and improving the robustness of the facial expression recognition network.Type: ApplicationFiled: September 27, 2021Publication date: October 13, 2022Applicants: Chongqing University, University of Electronic Science and Technology of China, Dibi (Chongqing) Intelligent Technology Research Institute Co., Ltd., Star Institute of Intelligent SystemsInventors: Yongduan Song, Feng Yang, Rui Li, Yiwen Zhang, Haoyuan Zhong, Jian Zhang, Shengtao Pan, Siyu Li, Zhengtao Yu
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Publication number: 20220004693Abstract: The present disclosure relates to a chip design layout process. More specifically, the present disclosure is directed to an incremental routing-based pin assignment technique. One example method generally includes: performing routing and pin assignment for a chip design layout, one or more objects of the chip design layout being associated with a routing engine and a pin assignment engine stored in memory; detecting a change associated with the one or more objects of the chip design layout; updating, via one or more processors, at least one of the routing engine or the pin assignment engine stored in the memory in response to the detected change and based on the association between the one or more objects and the routing engine or pin assignment engine; and performing another routing and pin assignment based on the updated at least one of the routing engine or the pin assignment engine.Type: ApplicationFiled: July 2, 2021Publication date: January 6, 2022Applicant: Synopsys, Inc.Inventor: Zhengtao YU
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Publication number: 20210390241Abstract: A method includes receiving a netlist for a chip including a bus and determining, by one or more processors and based on the netlist, a first routing topology for the bus and through a routing region of the chip by comparing a demand of the bus to a capacity of a plurality of cells of the routing region. The method also includes generating a layout for the chip based on the first routing topology.Type: ApplicationFiled: June 11, 2021Publication date: December 16, 2021Inventors: Zhengtao YU, Balkrishna RASHINGKAR, David PEART, Douglas CHANG, Yiding HAN
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Patent number: 9147030Abstract: Systems and techniques for multiple-instantiated-module (MIM)-aware pin assignment are described. An aggregate cost function can be determined, wherein the aggregate cost function is aggregated across all instances of an MIM for placing a pin at a particular location on the boundary of the MIM. The aggregate cost function can then be used by a pin assignment engine to place the pin in the MIM. A pin assignment engine can place one pin at a time, or place multiple pins at a time by trying to optimize the aggregate cost over multiple pins. Some embodiments can propagate pin-alignment constraints through one or more instances of one or more MIMs in the circuit design layout, and then perform pin assignment while observing the pin-alignment constraints. In some embodiments, pin assignment can be performed on MIMs in decreasing order of the number of pin-alignment constraints that are imposed on the MIMs.Type: GrantFiled: July 8, 2014Date of Patent: September 29, 2015Assignee: SYNOPSYS, INC.Inventor: Zhengtao Yu
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Patent number: 9064082Abstract: Methods and apparatuses are described for creating, editing, and viewing a floorplan of a circuit design. Specifically, some embodiments enable a user to perform a graphical operation at an inference point in a circuit design layout, wherein the location of the inference point is determined based on existing graphical objects in the circuit design layout. Some embodiments substantially instantaneously update a congestion indicator in a circuit design layout in response to modifying the circuit design layout. Some embodiments substantially instantaneously update pin locations of a block or partition in response to changing the size or shape of the block or partition. Some embodiments enable a user to view a circuit design layout based on the logical hierarchy, and also based on at least one additional attribute type such as voltage, power, or clock domain.Type: GrantFiled: October 8, 2014Date of Patent: June 23, 2015Assignee: SYNOPSYS, INC.Inventor: Zhengtao Yu
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Publication number: 20150026656Abstract: Methods and apparatuses are described for creating, editing, and viewing a floorplan of a circuit design. Specifically, some embodiments enable a user to perform a graphical operation at an inference point in a circuit design layout, wherein the location of the inference point is determined based on existing graphical objects in the circuit design layout. Some embodiments substantially instantaneously update a congestion indicator in a circuit design layout in response to modifying the circuit design layout. Some embodiments substantially instantaneously update pin locations of a block or partition in response to changing the size or shape of the block or partition. Some embodiments enable a user to view a circuit design layout based on the logical hierarchy, and also based on at least one additional attribute type such as voltage, power, or clock domain.Type: ApplicationFiled: October 8, 2014Publication date: January 22, 2015Inventor: Zhengtao Yu
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Publication number: 20140325467Abstract: Systems and techniques for multiple-instantiated-module (MIM)-aware pin assignment are described. An aggregate cost function can be determined, wherein the aggregate cost function is aggregated across all instances of an MIM for placing a pin at a particular location on the boundary of the MIM. The aggregate cost function can then be used by a pin assignment engine to place the pin in the MIM. A pin assignment engine can place one pin at a time, or place multiple pins at a time by trying to optimize the aggregate cost over multiple pins. Some embodiments can propagate pin-alignment constraints through one or more instances of one or more MIMs in the circuit design layout, and then perform pin assignment while observing the pin-alignment constraints. In some embodiments, pin assignment can be performed on MIMs in decreasing order of the number of pin-alignment constraints that are imposed on the MIMs.Type: ApplicationFiled: July 8, 2014Publication date: October 30, 2014Inventor: Zhengtao Yu
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Patent number: 8806407Abstract: Systems and techniques for multiple-instantiated-module (MIM)-aware pin assignment are described. An aggregate cost function can be determined, wherein the aggregate cost function is aggregated across all instances of an MIM for placing a pin at a particular location on the boundary of the MIM. The aggregate cost function can then be used by a pin assignment engine to place the pin in the MIM. A pin assignment engine can place one pin at a time, or place multiple pins at a time by trying to optimize the aggregate cost over multiple pins. Some embodiments can propagate pin-alignment constraints through one or more instances of one or more MIMs in the circuit design layout, and then perform pin assignment while observing the pin-alignment constraints. In some embodiments, pin assignment can be performed on MIMs in decreasing order of the number of pin-alignment constraints that are imposed on the MIMs.Type: GrantFiled: January 29, 2013Date of Patent: August 12, 2014Assignee: Synopsys, Inc.Inventor: Zhengtao Yu
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Publication number: 20140189632Abstract: Systems and techniques for multiple-instantiated-module (MIM)-aware pin assignment are described. An aggregate cost function can be determined, wherein the aggregate cost function is aggregated across all instances of an MIM for placing a pin at a particular location on the boundary of the MIM. The aggregate cost function can then be used by a pin assignment engine to place the pin in the MIM. A pin assignment engine can place one pin at a time, or place multiple pins at a time by trying to optimize the aggregate cost over multiple pins. Some embodiments can propagate pin-alignment constraints through one or more instances of one or more MIMs in the circuit design layout, and then perform pin assignment while observing the pin-alignment constraints. In some embodiments, pin assignment can be performed on MIMs in decreasing order of the number of pin-alignment constraints that are imposed on the MIMs.Type: ApplicationFiled: January 29, 2013Publication date: July 3, 2014Applicant: SYNOPSYS, INC.Inventor: Zhengtao Yu