Abstract: Capabilities and features of a modem are specified in accordance with descriptions of applications to be executed on the modem. The specification of the modem using individual applications enables the verification of intended performance based on the individual applications, simplifying the testing and assuring of the modem. To that end, a method implemented by a cloud computing resource (CCR) includes receiving, by the CCR, a description of an application supported by a modem. A dataflow fragment (DFF) for the application is generated by the CCR and is stored by the CCR in a memory, The DFF is retrieved and provided to the modem based on a description of the modem.

Abstract: A system-on-chip includes a reconfigurable data interface to prepare data streams for execution patterns of a processing unit in a flexible compute accelerate system. An apparatus is provided that includes a first set of line buffers configured to store a plurality of data blocks from a memory of a system-on-chip and a field composition circuit configured to generate a plurality of data segments from each of the data blocks. The field composition circuit is reconfigurable to generate the data segments according to a plurality of reconfiguration schemes. The apparatus includes a second set of line buffers configured to communicate with the field composition circuit to store the plurality of data segments for each data block, and a switching circuit configured to generate from the plurality of data segments a plurality of data streams according to an execution pattern of a processing unit of the system-on-chip.

Abstract: The disclosure relates to technology for configuring programmable logic devices having multiple programmable hardware units configurable in one or more functional modes. The programmable hardware units are coupled to independent switch devices (e.g., multiplexers) that select configuration patterns stored in a common and shared configuration memory. The configuration memory includes a set of configuration registers to store the configuration patterns, which configuration patterns correspond to the one or more functional modes. The configuration registers may be addressed using an index of addresses stored in memory that identify a select line in one of the switch devices for a particular programmable hardware unit. Each select line in a switch device corresponds to a particular one of the configuration registers storing the configuration pattern. The addressed configuration register is accessed to retrieve the configuration pattern and configure the programmable hardware unit.

Abstract: A system-on-chip includes a reconfigurable data interface to prepare data streams for execution patterns of a processing unit in a flexible compute accelerate system. An apparatus is provided that includes a first set of line buffers configured to store a plurality of data blocks from a memory of a system-on-chip and a field composition circuit configured to generate a plurality of data segments from each of the data blocks. The field composition circuit is reconfigurable to generate the data segments according to a plurality of reconfiguration schemes. The apparatus includes a second set of line buffers configured to communicate with the field composition circuit to store the plurality of data segments for each data block, and a switching circuit configured to generate from the plurality of data segments a plurality of data streams according to an execution pattern of a processing unit of the system-on-chip.

Abstract: The disclosure relates to technology for configuring programmable logic devices having multiple programmable hardware units configurable in one or more functional modes. The programmable hardware units are coupled to independent switch devices (e.g., multiplexers) that select configuration patterns stored in a common and shared configuration memory. The configuration memory includes a set of configuration registers to store the configuration patterns, which configuration patterns correspond to the one or more functional modes. The configuration registers may be addressed using an index of addresses stored in memory that identify a select line in one of the switch devices for a particular programmable hardware unit. Each select line in a switch device corresponds to a particular one of the configuration registers storing the configuration pattern. The addressed configuration register is accessed to retrieve the configuration pattern and configure the programmable hardware unit.

Abstract: The disclosure relates to technology for configuring programmable logic devices having multiple programmable hardware units configurable in one or more functional modes. The programmable hardware units are coupled to independent switch devices (e.g., multiplexers) that select configuration patterns stored in a common and shared configuration memory. The configuration memory includes a set of configuration registers to store the configuration patterns, which configuration patterns correspond to the one or more functional modes. The configuration registers may be addressed using an index of addresses stored in memory that identify a select line in one of the switch devices for a particular programmable hardware unit. Each select line in a switch device corresponds to a particular one of the configuration registers storing the configuration pattern. The addressed configuration register is accessed to retrieve the configuration pattern and configure the programmable hardware unit.

Abstract: A method includes receiving, by a system on a chip (SoC) from a logically centralized controller, configuration information and reading, from a semantics aware storage module of the SoC, a data block in accordance with the configuration information. The method also includes performing scheduling to produce a schedule in accordance with the configuration information and writing the data block to an input data queue in accordance with the schedule to produce a stored data block. Additionally, the method includes writing a tag to an input tag queue to produce a stored tag, where the tag corresponds to the data block.

Abstract: An interleaver/de-interleaver that may be used for multiple interleaving algorithms and look up tables (LUTs) of one or more interleaving standards. In at least some embodiments, the interleaver/de-interleaver may comprise an initial value selector, offset selector, and a pruning adjuster coupled to a combining block. The interleaver/de-interleaver may further comprise a boundary regulator coupled to the combining block, wherein the boundary regulator is configurable to modify an output of the combining block according to one or more pre-determined rules. The interleaver/de-interleaver may further comprise a controller coupled to, at least, the initial value selector, the offset value selector, and the offset adjuster, whereby the interleaver/de-interleaver may be used to interleave or de-interleave a block of data in accordance with a plurality of interleaving algorithms.

Abstract: An interleaver/de-interleaver that may be used for multiple interleaving algorithms and look up tables (LUTs) of one or more interleaving standards. In at least some embodiments, the interleaver/de-interleaver may comprise an initial value selector, offset selector, and a pruning adjuster coupled to a combining block. The interleaver/de-interleaver may further comprise a boundary regulator coupled to the combining block, wherein the boundary regulator is configurable to modify an output of the combining block according to one or more pre-determined rules. The interleaver/de-interleaver may further comprise a controller coupled to, at least, the initial value selector, the offset value selector, and the offset adjuster, whereby the interleaver/de-interleaver may be used to interleave or de-interleave a block of data in accordance with a plurality of interleaving algorithms.

Abstract: A dot product operator (30) uses adder trees (10) of L-1 adders and no multiplication circuits, where L is the length of the parallel dot product operator. Exclusive-or gates 12 provide the function of multiplication by ±1, with the carry-in ports of adders (14, 16, 18, 20, 32, 34, 36, 42) being used to form the two's complement, resulting in an extremely efficient design in terms of area and power.

Abstract: A system and method for maintaining timing in a CDMA rake receiver has a global chip counter that counts CDMA signal chips as they arrive at the CDMA rake receiver. A local pseudo-noise (PN) sequence replica of the incoming CDMA signal is generated and used to perform a sliding window correlation of the locally generated PN sequence replica with the incoming signal to correlate the CDMA signal timing relative to stored CDMA signal chip counts. The PN sequence timing is maintained relative to GCC, which avoids having to keep track of absolute time within each Rake finger.

Abstract: Multiple PN sequences are generated in parallel using multiple LFSRs (10) or multiple mask circuits (40) coupled to a single LFSR. The offsets between PN sequences can be individually and independently set, either by setting the initial state in an LFSR (10) or setting a mask vector in a mask circuit (40). The LFSRs can be configured in real time to produce one or more blocks of PN sequence bits or to produce disjoint PN sequence bits. Zero insertion may be automatically generated in the LFSRs without additional mask circuitry. PN generating circuits may use either relative or absolute addressing, and may accommodate two levels of relative addressing. Further, one embodiment provides relative addressing without using masks.

Abstract: A circuit is designed with a plurality of logic circuits (370-374) for producing an offset state matrix. The circuit includes a first logic circuit (380-383) coupled to receive N elements of a respective row of a transition matrix and N elements of column of an input state matrix. The first logic circuit produces a multi-bit logical combination of corresponding bits of the respective row and the column. A second logic circuit (390) is coupled to receive the multi-bit logical combination and produces a respective element of the offset state matrix.

Abstract: A circuit is designed with a plurality of logic circuits (370-374) for producing an offset state matrix. The circuit includes a first logic circuit (380-383) coupled to receive N elements of a respective row of a transition matrix and N elements of column of an input state matrix. The first logic circuit produces a multi-bit logical combination of corresponding bits of the respective row and the column. A second logic circuit (390) is coupled to receive the multi-bit logical combination and produces a respective element of the offset state matrix.

Abstract: A circuit is designed to receive a plurality of index signals (320, 321). The circuit includes a memory circuit arranged to store a plurality of state vectors (400-403). A multiplex circuit (406) is coupled to the memory circuit. The multiplex circuit selectively produces one of the state vectors (408) in response to at least one of the index signals (320). A matrix generator circuit (410) is arranged to produce a variable matrix in response to at least another of the index signals (321). A logic circuit (600-602) is coupled to the multiplex circuit and the matrix generator circuit. The logic circuit is arranged to produce a logical combination (412) of the variable matrix and said one of the state vectors.