Patents by Inventor Zhenguo Jiang

Zhenguo Jiang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240152770
    Abstract: This application relates to the artificial intelligence field, and discloses a neural network search method and a related apparatus. The neural network search method includes: constructing attention heads in transformer layers by sampling a plurality of candidate operators during model search, to construct a plurality of candidate neural networks, and comparing performance of the plurality of candidate neural networks to select a target neural network with higher performance. In this application, a transformer model is constructed with reference to model search, so that a new attention structure with better performance than an original self-attention mechanism can be generated, and effect in a wide range of downstream tasks is significantly improved.
    Type: Application
    Filed: January 12, 2024
    Publication date: May 9, 2024
    Inventors: Hang XU, Xiaozhe REN, Yichun YIN, Li QIAN, Zhenguo LI, Xin JIANG, Jiahui GAO
  • Publication number: 20240105577
    Abstract: Methods, systems, apparatus, and articles of manufacture to produce integrated circuit packages with grounding members are disclosed. An example semiconductor die disclosed herein includes a semiconductor substrate, metal interconnects proximate a first side of the semiconductor substrate, a metal contact proximate a second side of the semiconductor substrate opposite the first side, a first grounding member extending from a grounding interconnect of the metal interconnects to a first distal point in the semiconductor substrate, and a second grounding member extending from the metal contact to a second distal point in the semiconductor substrate, the first distal point closer to the first side of the semiconductor substrate than the second distal point is to the first side of the semiconductor substrate.
    Type: Application
    Filed: September 27, 2022
    Publication date: March 28, 2024
    Inventors: Zhenguo Jiang, Zhiguo Qian, Jiwei Sun, Babita Dhayal
  • Patent number: 11937367
    Abstract: Disclosed herein are radio frequency (RF) front-end structures, as well as related methods and devices. In some embodiments, an RF front-end package may include an RF package substrate including an embedded passive circuit element. At least a portion of the embedded passive circuit element may be included in a metal layer of the RF package substrate. The RF package substrate may also include a ground plane in the metal layer.
    Type: Grant
    Filed: July 3, 2023
    Date of Patent: March 19, 2024
    Assignee: Intel Corporation
    Inventors: Sidharth Dalmia, Zhenguo Jiang, William J. Lambert, Kirthika Nahalingam, Swathi Vijayakumar
  • Publication number: 20230354508
    Abstract: Disclosed herein are radio frequency (RF) front-end structures, as well as related methods and devices. In some embodiments, an RF front-end package may include an RF package substrate including an embedded passive circuit element. At least a portion of the embedded passive circuit element may be included in a metal layer of the RF package substrate. The RF package substrate may also include a ground plane in the metal layer.
    Type: Application
    Filed: July 3, 2023
    Publication date: November 2, 2023
    Applicant: Intel Corporation
    Inventors: Sidharth Dalmia, Zhenguo Jiang, William J. Lambert, Kirthika Nahalingam, Swathi Vijayakumar
  • Patent number: 11804426
    Abstract: Disclosed herein are integrated circuit (IC) structures that may be included in package substrates. For example, disclosed herein are passive components in package substrate, wherein the passive components include at least one non-circular via and at least one pad in contact with the at least one non-circular via, and the passive components include an inductor or a capacitor. Other embodiments are also disclosed.
    Type: Grant
    Filed: July 19, 2021
    Date of Patent: October 31, 2023
    Assignee: Intel Corporation
    Inventors: Sanka Ganesan, William James Lambert, Zhichao Zhang, Sri Chaitra Jyotsna Chavali, Stephen Andrew Smith, Michael James Hill, Zhenguo Jiang
  • Patent number: 11729902
    Abstract: Disclosed herein are radio frequency (RF) front-end structures, as well as related methods and devices. In some embodiments, an RF front-end package may include an RF package substrate including an embedded passive circuit element. At least a portion of the embedded passive circuit element may be included in a metal layer of the RF package substrate. The RF package substrate may also include a ground plane in the metal layer.
    Type: Grant
    Filed: February 5, 2019
    Date of Patent: August 15, 2023
    Assignee: Intel Corporation
    Inventors: Sidharth Dalmia, Zhenguo Jiang, William James Lambert, Kirthika Nahalingam, Swathi Vijayakumar
  • Patent number: 11611164
    Abstract: A wide bandwidth signal connector plug, comprising a plurality of signal pins having a first anchor portion and a first mating portion, and a plurality of ground pins having a second anchor portion and a second mating portion. The plurality of ground pins is adjacent to the plurality of signal pins. The plurality of signal pins has a first thickness and the plurality of ground pins has a second thickness that is greater than the first thickness. The first anchor portion has a first width and the second anchor portion has a second width that is greater than the first width.
    Type: Grant
    Filed: June 27, 2019
    Date of Patent: March 21, 2023
    Assignee: Intel Corporation
    Inventors: Zhenguo Jiang, Omkar Karhade, Sri Chaitra Chavali, William Lambert, Zhichao Zhang, Mitul Modi
  • Patent number: 11482471
    Abstract: An integrated circuit package may be formed having a heat transfer fluid chamber, wherein the heat transfer fluid chamber may be positioned to allow a heat transfer fluid to directly contact an integrated circuit device within the integrated circuit package. In one embodiment, a first surface of the integrated circuit device may be electrically attached to a first substrate. The first substrate may then may be electrically attached to a second substrate, such that the integrated circuit device is between the first substrate and the second substrate. The second substrate may include a cavity, wherein the heat transfer fluid chamber may be formed between a second surface of the integrated circuit device and the cavity of the second substrate. Thus, at least a portion of a second surface of the integrated circuit device is exposed to the heat transfer fluid which flows into the heat transfer fluid chamber.
    Type: Grant
    Filed: February 27, 2019
    Date of Patent: October 25, 2022
    Assignee: Intel Corporation
    Inventors: Cheng Xu, Junnan Zhao, Zhimin Wan, Ying Wang, Yikang Deng, Chong Zhang, Jiwei Sun, Zhenguo Jiang, Kyu-Oh Lee
  • Publication number: 20210351116
    Abstract: Disclosed herein are integrated circuit (IC) structures that may be included in package substrates. For example, disclosed herein are passive components in package substrate, wherein the passive components include at least one non-circular via and at least one pad in contact with the at least one non-circular via, and the passive components include an inductor or a capacitor. Other embodiments are also disclosed.
    Type: Application
    Filed: July 19, 2021
    Publication date: November 11, 2021
    Applicant: Intel Corporation
    Inventors: Sanka Ganesan, William James Lambert, Zhichao Zhang, Sri Chaitra Jyotsna Chavali, Stephen Andrew Smith, Michael James Hill, Zhenguo Jiang
  • Publication number: 20210305138
    Abstract: Embodiments disclosed herein include electronic packaged assemblies. In an embodiment, an electronic package comprises first and second surfaces. The second surface has a land pad in a land pad opening. The land pad is spaced away from the land pad opening by an outer gap. The land pad is a closed loop. In an embodiment, the electronic package is electrically coupled to a socket. The socket has an interconnect with a first connector and a second connector. The first connector of the interconnect is directly coupled to at least one portion of the closed loop. In an embodiment, when the first connector is coupled to at least two or more portions of the closed loop, the portions are spaced away from each other by a portion of the inner or outer gap. The closed loop comprises a conductive line continuously extending from a first end to a second end.
    Type: Application
    Filed: March 24, 2020
    Publication date: September 30, 2021
    Inventors: Zhichao ZHANG, Zhenguo JIANG, Haifa HARIRI, Kemal AYGÜN, Sriram SRINIVASAN
  • Patent number: 11107757
    Abstract: Disclosed herein are integrated circuit (IC) structures that may be included in package substrates. For example, disclosed herein are passive components in package substrate, wherein the passive components include at least one non-circular via and at least one pad in contact with the at least one non-circular via, and the passive components include an inductor or a capacitor. Other embodiments are also disclosed.
    Type: Grant
    Filed: April 22, 2020
    Date of Patent: August 31, 2021
    Assignee: Intel Corporation
    Inventors: Sanka Ganesan, William James Lambert, Zhichao Zhang, Sri Chaitra Jyotsna Chavali, Stephen Andrew Smith, Michael James Hill, Zhenguo Jiang
  • Publication number: 20200412041
    Abstract: A wide bandwidth signal connector plug, comprising a plurality of signal pins having a first anchor portion and a first mating portion, and a plurality of ground pins having a second anchor portion and a second mating portion. The plurality of ground pins is adjacent to the plurality of signal pins. The plurality of signal pins has a first thickness and the plurality of ground pins has a second thickness that is greater than the first thickness. The first anchor portion has a first width and the second anchor portion has a second width that is greater than the first width.
    Type: Application
    Filed: June 27, 2019
    Publication date: December 31, 2020
    Inventors: Zhenguo Jiang, Omkar Karhade, Sri Chaitra Chavali, William Lambert, Zhichao Zhang, Mitul Modi
  • Publication number: 20200273776
    Abstract: An integrated circuit package may be formed having a heat transfer fluid chamber, wherein the heat transfer fluid chamber may be positioned to allow a heat transfer fluid to directly contact an integrated circuit device within the integrated circuit package. In one embodiment, a first surface of the integrated circuit device may be electrically attached to a first substrate. The first substrate may then may be electrically attached to a second substrate, such that the integrated circuit device is between the first substrate and the second substrate. The second substrate may include a cavity, wherein the heat transfer fluid chamber may be formed between a second surface of the integrated circuit device and the cavity of the second substrate. Thus, at least a portion of a second surface of the integrated circuit device is exposed to the heat transfer fluid which flows into the heat transfer fluid chamber.
    Type: Application
    Filed: February 27, 2019
    Publication date: August 27, 2020
    Applicant: Intel Corporation
    Inventors: Cheng Xu, Junnan Zhao, Zhimin Wan, Ying Wang, Yikang Deng, Chong Zhang, Jiwei Sun, Zhenguo Jiang, Kyu-Oh Lee
  • Publication number: 20200253040
    Abstract: Disclosed herein are radio frequency (RF) front-end structures, as well as related methods and devices. In some embodiments, an RF front-end package may include an RF package substrate including an embedded passive circuit element. At least a portion of the embedded passive circuit element may be included in a metal layer of the RF package substrate. The RF package substrate may also include a ground plane in the metal layer.
    Type: Application
    Filed: February 5, 2019
    Publication date: August 6, 2020
    Applicant: Intel Corporation
    Inventors: Sidharth Dalmia, Zhenguo Jiang, William James Lambert, Kirthika Nahalingam, Swathi Vijayakumar
  • Publication number: 20200251411
    Abstract: Disclosed herein are integrated circuit (IC) structures that may be included in package substrates. For example, disclosed herein are passive components in package substrate, wherein the passive components include at least one non-circular via and at least one pad in contact with the at least one non-circular via, and the passive components include an inductor or a capacitor. Other embodiments are also disclosed.
    Type: Application
    Filed: April 22, 2020
    Publication date: August 6, 2020
    Applicant: Intel Corporation
    Inventors: Sanka Ganesan, William James Lambert, Zhichao Zhang, Sri Chaitra Jyotsna Chavali, Stephen Andrew Smith, Michael James Hill, Zhenguo Jiang
  • Publication number: 20200243956
    Abstract: An RF chip package comprises a housing and one or more conductive contacts designed to electrically connect the RF chip package to other conductive contacts. The housing includes a first substrate, a 3-D antenna on the first substrate, and a second substrate. The second substrate includes a plurality of semiconductor devices and is bonded to the first substrate. An interconnect structure allows for electrical connection between the first and second substrates. In some cases, the first substrate is flip-chip bonded to the second substrate or is otherwise connected to the second substrate by an array of solder balls. By integrating both the 3-D antenna and RF circuitry together in the same chip package, costs are minimized while bandwidth is greatly improved compared to a separately machined 3-D antenna.
    Type: Application
    Filed: January 26, 2019
    Publication date: July 30, 2020
    Applicant: INTEL CORPORATION
    Inventors: ZHENGUO JIANG, OMKAR KARHADE, SRICHAITRA CHAVALI, ZHICHAO ZHANG, JIMIN YAO, STEPHEN SMITH, XIAOQIAN LI, ROBERT L. SANKMAN
  • Patent number: 10672693
    Abstract: Disclosed herein are integrated circuit (IC) structures that may be included in package substrates. For example, disclosed herein are passive components in package substrate, wherein the passive components include at least one non-circular via and at least one pad in contact with the at least one non-circular via, and the passive components include an inductor or a capacitor. Other embodiments are also disclosed.
    Type: Grant
    Filed: April 3, 2018
    Date of Patent: June 2, 2020
    Assignee: Intel Corporation
    Inventors: Sanka Ganesan, William James Lambert, Zhichao Zhang, Sri Chaitra Jyotsna Chavali, Stephen Andrew Smith, Michael James Hill, Zhenguo Jiang
  • Publication number: 20190304887
    Abstract: Disclosed herein are integrated circuit (IC) structures that may be included in package substrates. For example, disclosed herein are passive components in package substrate, wherein the passive components include at least one non-circular via and at least one pad in contact with the at least one non-circular via, and the passive components include an inductor or a capacitor. Other embodiments are also disclosed.
    Type: Application
    Filed: April 3, 2018
    Publication date: October 3, 2019
    Applicant: Intel Corporation
    Inventors: Sanka Ganesan, William James Lambert, Zhichao Zhang, Sri Chaitra Jyotsna Chavali, Stephen Andrew Smith, Michael James Hill, Zhenguo Jiang