Patents by Inventor Zhenguo Jiang
Zhenguo Jiang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 12003023Abstract: An RF chip package comprises a housing and one or more conductive contacts designed to electrically connect the RF chip package to other conductive contacts. The housing includes a first substrate, a 3-D antenna on the first substrate, and a second substrate. The second substrate includes a plurality of semiconductor devices and is bonded to the first substrate. An interconnect structure allows for electrical connection between the first and second substrates. In some cases, the first substrate is flip-chip bonded to the second substrate or is otherwise connected to the second substrate by an array of solder balls. By integrating both the 3-D antenna and RF circuitry together in the same chip package, costs are minimized while bandwidth is greatly improved compared to a separately machined 3-D antenna.Type: GrantFiled: January 26, 2019Date of Patent: June 4, 2024Assignee: Intel CorporationInventors: Zhenguo Jiang, Omkar Karhade, Srichaitra Chavali, Zhichao Zhang, Jimin Yao, Stephen Smith, Xiaoqian Li, Robert Sankman
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Publication number: 20240164010Abstract: Disclosed herein are radio frequency (RF) front-end structures, as well as related methods and devices. In some embodiments, an RF front-end package may include an RF package substrate including an embedded passive circuit element. At least a portion of the embedded passive circuit element may be included in a metal layer of the RF package substrate. The RF package substrate may also include a ground plane in the metal layer.Type: ApplicationFiled: January 22, 2024Publication date: May 16, 2024Applicant: Intel CorporationInventors: Sidharth Dalmia, Zhenguo Jiang, William J. Lambert, Kirthika Nahalingam, Swathi Vijayakumar
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Publication number: 20240105577Abstract: Methods, systems, apparatus, and articles of manufacture to produce integrated circuit packages with grounding members are disclosed. An example semiconductor die disclosed herein includes a semiconductor substrate, metal interconnects proximate a first side of the semiconductor substrate, a metal contact proximate a second side of the semiconductor substrate opposite the first side, a first grounding member extending from a grounding interconnect of the metal interconnects to a first distal point in the semiconductor substrate, and a second grounding member extending from the metal contact to a second distal point in the semiconductor substrate, the first distal point closer to the first side of the semiconductor substrate than the second distal point is to the first side of the semiconductor substrate.Type: ApplicationFiled: September 27, 2022Publication date: March 28, 2024Inventors: Zhenguo Jiang, Zhiguo Qian, Jiwei Sun, Babita Dhayal
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Patent number: 11937367Abstract: Disclosed herein are radio frequency (RF) front-end structures, as well as related methods and devices. In some embodiments, an RF front-end package may include an RF package substrate including an embedded passive circuit element. At least a portion of the embedded passive circuit element may be included in a metal layer of the RF package substrate. The RF package substrate may also include a ground plane in the metal layer.Type: GrantFiled: July 3, 2023Date of Patent: March 19, 2024Assignee: Intel CorporationInventors: Sidharth Dalmia, Zhenguo Jiang, William J. Lambert, Kirthika Nahalingam, Swathi Vijayakumar
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Publication number: 20230354508Abstract: Disclosed herein are radio frequency (RF) front-end structures, as well as related methods and devices. In some embodiments, an RF front-end package may include an RF package substrate including an embedded passive circuit element. At least a portion of the embedded passive circuit element may be included in a metal layer of the RF package substrate. The RF package substrate may also include a ground plane in the metal layer.Type: ApplicationFiled: July 3, 2023Publication date: November 2, 2023Applicant: Intel CorporationInventors: Sidharth Dalmia, Zhenguo Jiang, William J. Lambert, Kirthika Nahalingam, Swathi Vijayakumar
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Patent number: 11804426Abstract: Disclosed herein are integrated circuit (IC) structures that may be included in package substrates. For example, disclosed herein are passive components in package substrate, wherein the passive components include at least one non-circular via and at least one pad in contact with the at least one non-circular via, and the passive components include an inductor or a capacitor. Other embodiments are also disclosed.Type: GrantFiled: July 19, 2021Date of Patent: October 31, 2023Assignee: Intel CorporationInventors: Sanka Ganesan, William James Lambert, Zhichao Zhang, Sri Chaitra Jyotsna Chavali, Stephen Andrew Smith, Michael James Hill, Zhenguo Jiang
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Patent number: 11729902Abstract: Disclosed herein are radio frequency (RF) front-end structures, as well as related methods and devices. In some embodiments, an RF front-end package may include an RF package substrate including an embedded passive circuit element. At least a portion of the embedded passive circuit element may be included in a metal layer of the RF package substrate. The RF package substrate may also include a ground plane in the metal layer.Type: GrantFiled: February 5, 2019Date of Patent: August 15, 2023Assignee: Intel CorporationInventors: Sidharth Dalmia, Zhenguo Jiang, William James Lambert, Kirthika Nahalingam, Swathi Vijayakumar
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Patent number: 11611164Abstract: A wide bandwidth signal connector plug, comprising a plurality of signal pins having a first anchor portion and a first mating portion, and a plurality of ground pins having a second anchor portion and a second mating portion. The plurality of ground pins is adjacent to the plurality of signal pins. The plurality of signal pins has a first thickness and the plurality of ground pins has a second thickness that is greater than the first thickness. The first anchor portion has a first width and the second anchor portion has a second width that is greater than the first width.Type: GrantFiled: June 27, 2019Date of Patent: March 21, 2023Assignee: Intel CorporationInventors: Zhenguo Jiang, Omkar Karhade, Sri Chaitra Chavali, William Lambert, Zhichao Zhang, Mitul Modi
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Patent number: 11482471Abstract: An integrated circuit package may be formed having a heat transfer fluid chamber, wherein the heat transfer fluid chamber may be positioned to allow a heat transfer fluid to directly contact an integrated circuit device within the integrated circuit package. In one embodiment, a first surface of the integrated circuit device may be electrically attached to a first substrate. The first substrate may then may be electrically attached to a second substrate, such that the integrated circuit device is between the first substrate and the second substrate. The second substrate may include a cavity, wherein the heat transfer fluid chamber may be formed between a second surface of the integrated circuit device and the cavity of the second substrate. Thus, at least a portion of a second surface of the integrated circuit device is exposed to the heat transfer fluid which flows into the heat transfer fluid chamber.Type: GrantFiled: February 27, 2019Date of Patent: October 25, 2022Assignee: Intel CorporationInventors: Cheng Xu, Junnan Zhao, Zhimin Wan, Ying Wang, Yikang Deng, Chong Zhang, Jiwei Sun, Zhenguo Jiang, Kyu-Oh Lee
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Publication number: 20210351116Abstract: Disclosed herein are integrated circuit (IC) structures that may be included in package substrates. For example, disclosed herein are passive components in package substrate, wherein the passive components include at least one non-circular via and at least one pad in contact with the at least one non-circular via, and the passive components include an inductor or a capacitor. Other embodiments are also disclosed.Type: ApplicationFiled: July 19, 2021Publication date: November 11, 2021Applicant: Intel CorporationInventors: Sanka Ganesan, William James Lambert, Zhichao Zhang, Sri Chaitra Jyotsna Chavali, Stephen Andrew Smith, Michael James Hill, Zhenguo Jiang
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Publication number: 20210305138Abstract: Embodiments disclosed herein include electronic packaged assemblies. In an embodiment, an electronic package comprises first and second surfaces. The second surface has a land pad in a land pad opening. The land pad is spaced away from the land pad opening by an outer gap. The land pad is a closed loop. In an embodiment, the electronic package is electrically coupled to a socket. The socket has an interconnect with a first connector and a second connector. The first connector of the interconnect is directly coupled to at least one portion of the closed loop. In an embodiment, when the first connector is coupled to at least two or more portions of the closed loop, the portions are spaced away from each other by a portion of the inner or outer gap. The closed loop comprises a conductive line continuously extending from a first end to a second end.Type: ApplicationFiled: March 24, 2020Publication date: September 30, 2021Inventors: Zhichao ZHANG, Zhenguo JIANG, Haifa HARIRI, Kemal AYGÜN, Sriram SRINIVASAN
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Patent number: 11107757Abstract: Disclosed herein are integrated circuit (IC) structures that may be included in package substrates. For example, disclosed herein are passive components in package substrate, wherein the passive components include at least one non-circular via and at least one pad in contact with the at least one non-circular via, and the passive components include an inductor or a capacitor. Other embodiments are also disclosed.Type: GrantFiled: April 22, 2020Date of Patent: August 31, 2021Assignee: Intel CorporationInventors: Sanka Ganesan, William James Lambert, Zhichao Zhang, Sri Chaitra Jyotsna Chavali, Stephen Andrew Smith, Michael James Hill, Zhenguo Jiang
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Publication number: 20200412041Abstract: A wide bandwidth signal connector plug, comprising a plurality of signal pins having a first anchor portion and a first mating portion, and a plurality of ground pins having a second anchor portion and a second mating portion. The plurality of ground pins is adjacent to the plurality of signal pins. The plurality of signal pins has a first thickness and the plurality of ground pins has a second thickness that is greater than the first thickness. The first anchor portion has a first width and the second anchor portion has a second width that is greater than the first width.Type: ApplicationFiled: June 27, 2019Publication date: December 31, 2020Inventors: Zhenguo Jiang, Omkar Karhade, Sri Chaitra Chavali, William Lambert, Zhichao Zhang, Mitul Modi
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Publication number: 20200273776Abstract: An integrated circuit package may be formed having a heat transfer fluid chamber, wherein the heat transfer fluid chamber may be positioned to allow a heat transfer fluid to directly contact an integrated circuit device within the integrated circuit package. In one embodiment, a first surface of the integrated circuit device may be electrically attached to a first substrate. The first substrate may then may be electrically attached to a second substrate, such that the integrated circuit device is between the first substrate and the second substrate. The second substrate may include a cavity, wherein the heat transfer fluid chamber may be formed between a second surface of the integrated circuit device and the cavity of the second substrate. Thus, at least a portion of a second surface of the integrated circuit device is exposed to the heat transfer fluid which flows into the heat transfer fluid chamber.Type: ApplicationFiled: February 27, 2019Publication date: August 27, 2020Applicant: Intel CorporationInventors: Cheng Xu, Junnan Zhao, Zhimin Wan, Ying Wang, Yikang Deng, Chong Zhang, Jiwei Sun, Zhenguo Jiang, Kyu-Oh Lee
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Publication number: 20200251411Abstract: Disclosed herein are integrated circuit (IC) structures that may be included in package substrates. For example, disclosed herein are passive components in package substrate, wherein the passive components include at least one non-circular via and at least one pad in contact with the at least one non-circular via, and the passive components include an inductor or a capacitor. Other embodiments are also disclosed.Type: ApplicationFiled: April 22, 2020Publication date: August 6, 2020Applicant: Intel CorporationInventors: Sanka Ganesan, William James Lambert, Zhichao Zhang, Sri Chaitra Jyotsna Chavali, Stephen Andrew Smith, Michael James Hill, Zhenguo Jiang
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Publication number: 20200253040Abstract: Disclosed herein are radio frequency (RF) front-end structures, as well as related methods and devices. In some embodiments, an RF front-end package may include an RF package substrate including an embedded passive circuit element. At least a portion of the embedded passive circuit element may be included in a metal layer of the RF package substrate. The RF package substrate may also include a ground plane in the metal layer.Type: ApplicationFiled: February 5, 2019Publication date: August 6, 2020Applicant: Intel CorporationInventors: Sidharth Dalmia, Zhenguo Jiang, William James Lambert, Kirthika Nahalingam, Swathi Vijayakumar
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Publication number: 20200243956Abstract: An RF chip package comprises a housing and one or more conductive contacts designed to electrically connect the RF chip package to other conductive contacts. The housing includes a first substrate, a 3-D antenna on the first substrate, and a second substrate. The second substrate includes a plurality of semiconductor devices and is bonded to the first substrate. An interconnect structure allows for electrical connection between the first and second substrates. In some cases, the first substrate is flip-chip bonded to the second substrate or is otherwise connected to the second substrate by an array of solder balls. By integrating both the 3-D antenna and RF circuitry together in the same chip package, costs are minimized while bandwidth is greatly improved compared to a separately machined 3-D antenna.Type: ApplicationFiled: January 26, 2019Publication date: July 30, 2020Applicant: INTEL CORPORATIONInventors: ZHENGUO JIANG, OMKAR KARHADE, SRICHAITRA CHAVALI, ZHICHAO ZHANG, JIMIN YAO, STEPHEN SMITH, XIAOQIAN LI, ROBERT L. SANKMAN
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Patent number: 10672693Abstract: Disclosed herein are integrated circuit (IC) structures that may be included in package substrates. For example, disclosed herein are passive components in package substrate, wherein the passive components include at least one non-circular via and at least one pad in contact with the at least one non-circular via, and the passive components include an inductor or a capacitor. Other embodiments are also disclosed.Type: GrantFiled: April 3, 2018Date of Patent: June 2, 2020Assignee: Intel CorporationInventors: Sanka Ganesan, William James Lambert, Zhichao Zhang, Sri Chaitra Jyotsna Chavali, Stephen Andrew Smith, Michael James Hill, Zhenguo Jiang
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Publication number: 20190304887Abstract: Disclosed herein are integrated circuit (IC) structures that may be included in package substrates. For example, disclosed herein are passive components in package substrate, wherein the passive components include at least one non-circular via and at least one pad in contact with the at least one non-circular via, and the passive components include an inductor or a capacitor. Other embodiments are also disclosed.Type: ApplicationFiled: April 3, 2018Publication date: October 3, 2019Applicant: Intel CorporationInventors: Sanka Ganesan, William James Lambert, Zhichao Zhang, Sri Chaitra Jyotsna Chavali, Stephen Andrew Smith, Michael James Hill, Zhenguo Jiang