Abstract: A semiconductor device includes an insulated-gate field-effect transistor which is disposed on a semiconductor substrate having an element formation plane in a (110) plane direction, and which has a channel length direction in a <?110 > direction, and a first element isolation insulation film which is buried in a trench in an element isolation region of the semiconductor substrate and has a positive expansion coefficient, the first element isolation insulation film applying a compressive stress by operation heat to the insulated-gate field-effect transistor in the channel length direction.

Abstract: A semiconductor device includes a first insulated-gate field-effect transistor which is disposed on a semiconductor substrate having an element formation plane in a (110) plane direction, and which has a channel length direction in a <?110> direction, a second insulated-gate field-effect transistor which is disposed on the semiconductor substrate, has a channel length direction in the <?110> direction, and neighbors the first insulated-gate field-effect transistor in the channel length direction, and a first liner insulation film which is provided in a manner to cover the first and second insulated-gate field-effect transistors, the first liner insulation film including a piezomaterial, having a positive expansion coefficient, and applying a compressive stress by operation heat to the first and second insulated-gate field-effect transistors in the channel length direction.

Abstract: A semiconductor device includes an N-type insulated-gate field-effect transistor including a first insulating layer that is provided along side walls of a gate electrode, has a negative thermal expansion coefficient, and applies a tensile stress to a channel region of the N-type insulated-gate field-effect transistor. The device also includes a P-type insulated-gate field-effect transistor including a second insulating layer that is provided along side walls of a gate electrode, has a positive thermal expansion coefficient, and applies a compression stress to a channel region of the P-type insulated-gate field-effect transistor.

Abstract: A semiconductor device includes a gate insulation film that is formed of pyroceramics including an amorphous matrix layer, which is provided on a major surface of a silicon substrate, and crystalline phases lines with a high dielectric constant, which are dispersed in the amorphous matrix layer. The semiconductor device further includes a gate electrode that is provided on the gate insulation film.

Abstract: A semiconductor device includes a first insulated-gate field-effect transistor which is disposed on a semiconductor substrate having an element formation plane in a (110) plane direction, and which has a channel length direction in a <?110> direction, a second insulated-gate field-effect transistor which is disposed on the semiconductor substrate, has a channel length direction in the <?110> direction, and neighbors the first insulated-gate field-effect transistor in the channel length direction, and a first liner insulation film which is provided in a manner to cover the first and second insulated-gate field-effect transistors, the first liner insulation film including a piezomaterial, having a positive expansion coefficient, and applying a compressive stress by operation heat to the first and second insulated-gate field-effect transistors in the channel length direction.

Abstract: A semiconductor device includes an insulated-gate field-effect transistor which is disposed on a semiconductor substrate having an element formation plane in a (110) plane direction, and which has a channel length direction in a <?110> direction, and a first element isolation insulation film which is buried in a trench in an element isolation region of the semiconductor substrate and has a positive expansion coefficient, the first element isolation insulation film applying a compressive stress by operation heat to the insulated-gate field-effect transistor in the channel length direction.

Abstract: A semiconductor device includes an insulated-gate field-effect transistor including a gate electrode provided on a semiconductor substrate, and a source and a drain provided spaced apart in the semiconductor substrate in a manner to sandwich the gate electrode, the insulated-gate field-effect transistor having electrons or holes as carriers, and an element isolation insulation film having a negative expansion coefficient, which is disposed in the semiconductor substrate in an element isolation region along a channel width direction and a channel length direction in a manner to surround the insulated-gate field-effect transistor, the element isolation insulation film applying a tensile stress by operation heat to the insulated-gate field-effect transistor in two axial directions that are the channel width direction and the channel length direction.

Abstract: A semiconductor device comprises an N-type insulated-gate field-effect transistor including a first insulating layer that is provided along side walls of a gate electrode, has a negative thermal expansion coefficient, and applies a tensile stress to a channel region of the N-type insulated-gate field-effect transistor. The device also comprises a P-type insulated-gate field-effect transistor including a second insulating layer that is provided along side walls of a gate electrode, has a positive thermal expansion coefficient, and applies a compression stress to a channel region of the P-type insulated-gate field-effect transistor.

Abstract: A semiconductor device according to an embodiment includes an insulated-gate field-effect transistor including a gate insulation film provided on a major surface of a semiconductor substrate, a gate electrode provided on the gate insulation film, and a source and a drain provided spaced apart in the semiconductor substrate such that the gate electrode is interposed between the source and the drain, a first contact wiring line which is provided on the source, a second contact wiring line which is provided on the drain, and a piezoelectric layer which is provided to cover the gate electrode and has one end and the other end connected between the first and second contact wiring lines.

Abstract: A semiconductor device comprises an N-type insulated-gate field-effect transistor including a first insulating layer that is provided along side walls of a gate electrode, has a negative thermal expansion coefficient, and applies a tensile stress to a channel region of the N-type insulated-gate field-effect transistor. The device also comprises a P-type insulated-gate field-effect transistor including a second insulating layer that is provided along side walls of a gate electrode, has a positive thermal expansion coefficient, and applies a compression stress to a channel region of the P-type insulated-gate field-effect transistor.

Abstract: A semiconductor device according to an embodiment includes an insulated-gate field-effect transistor including a gate insulation film provided on a major surface of a semiconductor substrate, a gate electrode provided on the gate insulation film, and a source and a drain provided spaced apart in the semiconductor substrate such that the gate electrode is interposed between the source and the drain, a first contact wiring line which is provided on the source, a second contact wiring line which is provided on the drain, and a piezoelectric layer which is provided to cover the gate electrode and has one end and the other end connected between the first and second contact wiring lines.

Abstract: A semiconductor device comprises an N-type insulated-gate field-effect transistor including a first insulating layer that is provided along side walls of a gate electrode, has a negative thermal expansion coefficient, and applies a tensile stress to a channel region of the N-type insulated-gate field-effect transistor. The device also comprises a P-type insulated-gate field-effect transistor including a second insulating layer that is provided along side walls of a gate electrode, has a positive thermal expansion coefficient, and applies a compression stress to a channel region of the P-type insulated-gate field-effect transistor.

Abstract: A semiconductor device includes a gate insulation film that is formed of pyroceramics including an amorphous matrix layer, which is provided on a major surface of a silicon substrate, and crystalline phases lines with a high dielectric constant, which are dispersed in the amorphous matrix layer. The semiconductor device further includes a gate electrode that is provided on the gate insulation film.