Abstract: A fully differential level conversion circuit includes a positive signal branch, a negative signal branch and a coupling branch. The negative signal branch has identical structural features with the positive signal branch, which includes a drive terminal and a load terminal, an external fully differential signal is inputted to the drive terminals of the positive signal branch and the negative signal branch correspondingly. The coupling branch includes a first group of active couplers which forms a dual structure with the drive terminal of the positive signal branch and a second group of active couplers which form another dual structure with the drive terminal of the negative signal branch, both of which are connected between the drive terminals and load terminals. The fully differential level conversion circuit realizes applications in the signal processing process which has low power consumption and high-speed, and improves duty cycle of the output signal.

Abstract: A sample and hold switch circuit includes a clock generation sub-circuit, a gate voltage bootstrap unit, a sampling Field Effect Transistor, a holding capacitor and a substrate selection sub-circuit which is connected with a signal input terminal, a signal output terminal and a substrate of the sampling Field Effect Transistor and arranged for selecting the signal input terminal or the signal output terminal to connect with the substrate of the sampling Field Effect Transistor according to the voltages of the analog signal inputted and the analog signal outputted. The sample and hold switch circuit reduces nonlinearity of the sampling Field Effect Transistor caused by its gate-source voltage changing with input signal, and eliminates bulk effect of the sampling Field Effect Transistor, thereby improving linearity of the sampling Field Effect Transistor, and extending dynamic range of the sample and hold switch circuit.

Abstract: A signal amplitude detection circuit includes a detector and a trimming algorithm module, and the detector having a preset baseline threshold reference value and an output terminal connected with the trimming algorithm module which is arranged for recording and decoding an output result of the detector to output an amplitude code value, and generating a control signal for controlling the baseline threshold reference value rise to a power supply level from a ground level or drop to the ground level from the power supply level, and the output result of the detector being “1” if a crossover occurs between the baseline threshold reference value and the detected signal; otherwise being “0”. The signal amplitude detection circuit detects the signal amplitude in a digital way, which has simpler structure, lower power consumption, reduced size of chips, and stable and accurate detection result without PVT drift.

Abstract: A quick comparison circuit includes a cascaded N-stage operational amplifier, a flip-latch, a biasing circuit, and a control signal generating circuit, with N?2, and two differential signals to be compared being inputted to an input terminal of a first stage operational amplifier, an output terminal of a Nth stage operational amplifier being connected with an input terminal of the flip-latch, the biasing circuit supplying a biasing current to each stage operational amplifier, the control signal generating circuit being connected with the N-stage operational amplifier and the flip-latch respectively to supply a working time sequence and a reset control signal for them, and each stage operational amplifier having the same structure. This circuit has high gain and improved comparison speed.

Abstract: A smart mobile terminal remote control system includes a smart mobile terminal, a displaying device, a remote controller and a controller, the displaying device is configured to display an operation interface of the smart mobile terminal in real time, the controller is connected to the smart mobile terminal and the remote controller respectively and configured to emit an infrared light and receive the infrared light reflected by the remote controller, obtain information of the remote controller according to the infrared light received, generate a control command according to the information, and send the control command to the smart mobile terminal which responds to the control command. The smart mobile terminal remote control system makes the smart mobile terminal transfer data to other displaying devices smoothly and get a better displaying effect.

Abstract: A locking detection circuit for CDR circuits includes a first frequency divider, a second frequency divider, a first sampler, a second sampler, and a locking detector, with a data signal outputted by a CDR circuit being inputted to the first frequency divider and the first sampler respectively, the first frequency divider being connected with the first sampler, a clock pulse outputted by the CDR circuit being inputted to the second frequency divider and the second sampler respectively, output terminals of the first and second samplers being connected with the locking detector which is for detecting if rising edges of the data signal outputted and the clock pulse outputted are aligned, and then outputting a detection result. The circuit size and power consumption is reduced, and it is applicable to spread spectrum carrier with high data rate over 1 Gbps and with any protocol, whose application scope is broadened.

Abstract: A high-precision oscillator includes a voltage reference module which includes multiple measured Field Effect Transistors and arranged for detecting process corners for the measured Field Effect Transistors to generate a reference voltage containing process corner information of the measured Field Effect Transistors, a compensation current generating module which is arranged for receiving the reference voltage, making a temperature compensation for the reference voltage, and generating a compensation current which includes both the process compensation and temperature compensation, and a ring oscillator which is arranged for receiving the compensation current and outputting a clock with stable frequency.

Abstract: An LC oscillator process compensation circuit includes an LC oscillator, a reference voltage terminal, a follower and a current auxiliary circuit, the LC oscillator includes a gain stage, an inductor and two voltage-controlled capacitors, the gain stage includes a first Field Effect Transistor, a second Field Effect Transistor, a third Field Effect Transistor and a fourth Field Effect Transistor, the current auxiliary circuit is connected with an external power source and the follower that connected with the reference voltage terminal to provide a working voltage for the LC oscillator, the follower includes a detection circuit to detecting current changes of the gain stage. The LC oscillator process compensation circuit has simple circuit structure and eliminates frequency changes of the LC oscillator caused by the process variations of the gain stage, thereby ensuring stability of the frequency of the LC oscillator, improving work precision and reducing design difficult.

Abstract: A sample and hold switch circuit includes a clock generation sub-circuit, a gate voltage bootstrap unit, a sampling Field Effect Transistor, a holding capacitor and a substrate selection sub-circuit which is connected with a signal input terminal, a signal output terminal and a substrate of the sampling Field Effect Transistor and arranged for selecting the signal input terminal or the signal output terminal to connect with the substrate of the sampling Field Effect Transistor according to the voltages of the analog signal inputted and the analog signal outputted. The sample and hold switch circuit reduces nonlinearity of the sampling Field Effect Transistor caused by its gate-source voltage changing with input signal, and eliminates bulk effect of the sampling Field Effect Transistor, thereby improving linearity of the sampling Field Effect Transistor, and extending dynamic range of the sample and hold switch circuit.

Abstract: A quick comparison circuit includes a cascaded N-stage operational amplifier, a flip-latch, a biasing circuit, and a control signal generating circuit, with N?2, and two differential signals to be compared being inputted to an input terminal of a first stage operational amplifier, an output terminal of a Nth stage operational amplifier being connected with an input terminal of the flip-latch, the biasing circuit supplying a biasing current to each stage operational amplifier, the control signal generating circuit being connected with the N-stage operational amplifier and the flip-latch respectively to supply a working time sequence and a reset control signal for them, and each stage operational amplifier having the same structure. This circuit has high gain and improved comparison speed.

Abstract: A fully differential level conversion circuit includes a positive signal branch, a negative signal branch and a coupling branch. The negative signal branch has identical structural features with the positive signal branch, which includes a drive terminal and a load terminal, an external fully differential signal is inputted to the drive terminals of the positive signal branch and the negative signal branch correspondingly. The coupling branch includes a first group of active couplers which forms a dual structure with the drive terminal of the positive signal branch and a second group of active couplers which form another dual structure with the drive terminal of the negative signal branch, both of which are connected between the drive terminals and load terminals. The fully differential level conversion circuit realizes applications in the signal processing process which has low power consumption and high-speed, and improves duty cycle of the output signal.

Abstract: A locking detection circuit for CDR circuits includes a first frequency divider, a second frequency divider, a first sampler, a second sampler, and a locking detector, with a data signal outputted by a CDR circuit being inputted to the first frequency divider and the first sampler respectively, the first frequency divider being connected with the first sampler, a clock pulse outputted by the CDR circuit being inputted to the second frequency divider and the second sampler respectively, output terminals of the first and second samplers being connected with the locking detector which is for detecting if rising edges of the data signal outputted and the clock pulse outputted are aligned, and then outputting a detection result. The circuit size and power consumption is reduced, and it is applicable to spread spectrum carrier with high data rate over 1 Gbps and with any protocol, whose application scope is broadened.

Abstract: A signal amplitude detection circuit includes a detector and a trimming algorithm module, and the detector having a preset baseline threshold reference value and an output terminal connected with the trimming algorithm module which is arranged for recording and decoding an output result of the detector to output an amplitude code value, and generating a control signal for controlling the baseline threshold reference value rise to a power supply level from a ground level or drop to the ground level from the power supply level, and the output result of the detector being “1” if a crossover occurs between the baseline threshold reference value and the detected signal; otherwise being “0”. The signal amplitude detection circuit detects the signal amplitude in a digital way, which has simpler structure, lower power consumption, reduced size of chips, and stable and accurate detection result without PVT drift.

Abstract: A high-precision oscillator includes a voltage reference module which includes multiple measured Field Effect Transistors and arranged for detecting process corners for the measured Field Effect Transistors to generate a reference voltage containing process corner information of the measured Field Effect Transistors, a compensation current generating module which is arranged for receiving the reference voltage, making a temperature compensation for the reference voltage, and generating a compensation current which includes both the process compensation and temperature compensation, and a ring oscillator which is arranged for receiving the compensation current and outputting a clock with stable frequency.

Abstract: An LC oscillator process compensation circuit includes an LC oscillator, a reference voltage terminal, a follower and a current auxiliary circuit, the LC oscillator includes a gain stage, an inductor and two voltage-controlled capacitors, the gain stage includes a first Field Effect Transistor, a second Field Effect Transistor, a third Field Effect Transistor and a fourth Field Effect Transistor, the current auxiliary circuit is connected with an external power source and the follower that connected with the reference voltage terminal to provide a working voltage for the LC oscillator, the follower includes a detection circuit to detecting current changes of the gain stage. The LC oscillator process compensation circuit has simple circuit structure and eliminates frequency changes of the LC oscillator caused by the process variations of the gain stage, thereby ensuring stability of the frequency of the LC oscillator, improving work precision and reducing design difficult.

Abstract: A method of storing and accessing an error correcting code in NAND Flash, includes utilizing n pages of a block of the NAND Flash as an extended space of a spare area, n?1, wherein when writing data, the data is stored in a data area of a sector, and when the error correcting code needs a space which has correcting capability larger than 16 bytes, first 16 bytes of the error correcting code is stored in the 16 bytes spare area, and the remaining of the error correcting code is stored in the extended space of the spare area corresponding to the sector. Therefore, the method develops new storing space for the error correcting code, arranges the error correcting code in sequence of data blocks in sub-space, and loads the error correcting code into system memory for the decoder before reading original data.

Abstract: A storage control system, for controlling data transmission between a computer and an external device, includes a USB interface connected to the computer, an external interface connected to the external device and a control module connected between the USB interface and the external interface. The control module includes a data transmission submodule transmitting data with the computer, a microcontroller controlling a work flow of the control module, a ROM connected to the microcontroller, a protocol resolution submodule resolving data, a protocol timing sequencer connected to the external interface for transforming protocols and a buffer connected between the protocol resolution submodule and the protocol timing sequencer for storing data. The ROM changes its code according to different external devices. The microcontroller controls a work flow of the control module according to the code of the ROM to realize functions of different external devices. The invention further provides a storage control method.

Abstract: A method of storing and accessing an error correcting code in NAND Flash, includes utilizing n pages of a block of the NAND Flash as an extended space of a spare area, n?1, wherein when writing data, the data is stored in a data area of a sector, and when the error correcting code needs a space which has correcting capability larger than 16 bytes, first 16 bytes of the error correcting code is stored in the 16 bytes spare area, and the remaining of the error correcting code is stored in the extended space of the spare area corresponding to the sector. Therefore, the method develops new storing space for the error correcting code, arranges the error correcting code in sequence of data blocks in sub-space, and loads the error correcting code into system memory for the decoder before reading original data.

Abstract: The existence of physicochemical variables in semiconductor components, such as the edge effect, the ion implantation, the surface state effect, and the variation in charge carrier mobility, is exploited in a method for manufacturing random serial number for integrated circuits. The physicochemical variables are measured with a high gain amplification circuit and then converted into digital signal. Owing to the randomness of variation of the measured physicochemical variables in semiconductor components, multiple random serial numbers are generated by using multiple amplification circuit units.