Abstract: The present application discloses a CMOS image sensor. A pixel cell circuit comprises a photodiode and a CMOS pixel readout circuit. The pixel cell circuit is formed on an SOI substrate, and the photodiode is formed on a bottom semiconductor substrate. The CMOS pixel readout circuit is formed on a top semiconductor substrate. A photo-induced carrier of the photodiode is connected to the CMOS pixel readout circuit by means of an electrotransfer structure passing through a dielectric buried layer. The present application also discloses a method for manufacturing a CMOS image sensor. The present application can increase a pixel cell density without reducing a photodiode area, thus achieving an ultra-high CMOS image sensor density and improving the device quality.

Abstract: The present application discloses a double-layer stacked CMOS image sensor, photo diode and transfer gate transistor of a pixel cell are formed on the first substrate sequentially along a longitudinal direction, and the other pixel transistors of the pixel cell are formed on the second substrate. The first substrate and the second substrate are packaged separately, and the second substrate is stacked on the top side of the first substrate instead of being in juxtaposition. Since the photo diode and the pixel transistors other than the transfer gate transistor of the pixel cell are located on two separate substrates respectively, the area of a photo diode region may be increased significantly, thereby greatly increasing full well capacitance of the image sensor and increasing a dynamic range, and reduce a dark current and image noise significantly, thereby improving the dark line noise and full well capacitance simultaneously.

Abstract: The present application provides a method for automatically detecting a wafer backside brightfield image anomaly, at least comprising: processing wafer backside brightfield images by means of histogram equalization, so as to obtain processed images; compiling statistics for a gray histogram of the processed images; calculating the number of abnormal pixels in each of the images; and providing a threshold, and highlighting the image with a score less than the threshold. In the present application, the wafer backside brightfield images are analyzed by means of image preprocessing and a specific calculation method, so as to quickly and automatically detect an abnormal wafer backside image.

Abstract: The disclosure discloses a method for forming a doped epitaxial layer of contact image sensor. Epitaxial growth is performed in times. After each time of epitaxial growth, trench isolation and ion implantation are performed to form deep and shallow trench isolation running through a large-thickness doped epitaxial layer. Through cyclic operation of epitaxial growth, trench isolation and ion implantation, the photoresist and hard mask required at each time do not need to be too thick. In the process of trench isolation and ion implantation, the photoresist and etching morphologies are good, such that the lag problem of the prepared contact image sensor is improved. By forming the large-thickness doped epitaxial layer by adopting the method for forming the doped epitaxial layer of the contact image sensor, a high-performance contact image sensor applicable to high quantum efficiency, small pixel size and near infrared/infrared can be prepared.

Abstract: The present disclosure provides a method for improving HDP filling defects through an STI etching process, comprises a wafer uniformly distributed with pixel areas and logical areas, and dividing the wafer into quadrants 1 to 4; placing the second quadrants in an etching chamber in a manner of facing to a cantilever of an etching machine; etching the wafer to form STI areas with the same depth in the pixel areas and the logical areas of the quadrants 1 to 4; removing the wafer from the etching machine and covering the STI areas of the pixel areas with a photoresist; placing the wafer on an electrostatic chuck of the etching chamber again, and enabling any quadrant except the second quadrant to face to the cantilever; continuously etching the STI areas of the logical areas of the quadrants 1 to 4 to form deep STI areas.

Abstract: The present disclosure provides a method for improving HDP filling defects through an STI etching process, comprises a wafer uniformly distributed with pixel areas and logical areas, and dividing the wafer into quadrants 1 to 4; placing the second quadrants in an etching chamber in a manner of facing to a cantilever of an etching machine; etching the wafer to form STI areas with the same depth in the pixel areas and the logical areas of the quadrants 1 to 4; removing the wafer from the etching machine and covering the STI areas of the pixel areas with a photoresist; placing the wafer on an electrostatic chuck of the etching chamber again, and enabling any quadrant except the second quadrant to face to the cantilever; continuously etching the STI areas of the logical areas of the quadrants 1 to 4 to form deep STI areas.

Abstract: An EBM variable-direction formation dynamic slicing method in cooperation with an 840D digital control system includes: creating a vertex array object, adjusting a projection matrix to a slice height, outputting a binary image of a two-dimensional cross-section; obtaining, by means of two-dimensional contour extraction, data of a contour line from the binary image, outputting coordinates of a closed contour, and connecting all adjacent coordinates into a straight line to form a closed curve; when a triangle tolerance is 1, dividing contour data into a straight line part and a curve part by taking a starting point of small straight lines with an angle of 140° therebetween as a dividing point, removing adjacent points, repeated points and internal points of a same straight line, and performing segmentation fitting on curve parts of the slice data, and then performing dynamic slicing through the 840D numerical control system.

Abstract: The disclosure discloses a method for forming a doped epitaxial layer of contact image sensor. Epitaxial growth is performed in times. After each time of epitaxial growth, trench isolation and ion implantation are performed to form deep and shallow trench isolation running through a large-thickness doped epitaxial layer. Through cyclic operation of epitaxial growth, trench isolation and ion implantation, the photoresist and hard mask required at each time do not need to be too thick. In the process of trench isolation and ion implantation, the photoresist and etching morphologies are good, such that the lag problem of the prepared contact image sensor is improved. By forming the large-thickness doped epitaxial layer by adopting the method for forming the doped epitaxial layer of the contact image sensor, a high-performance contact image sensor applicable to high quantum efficiency, small pixel size and near infrared/infrared can be prepared.

Abstract: A high voltage integrated circuit device includes a semiconductor substrate having a surface region with a contact region, which is coupled to a source/drain region. The device has a plasma enhanced oxide overlying the surface region, a stop layer overlying the plasma enhanced oxide, and a contact opening through a portion of the stop layer and through a portion of the plasma enhanced oxide layer. The contact opening exposes a portion of the contact region without damaging it. The device has a silicide layer overlying the contact region to form a silicided contact region and an interlayer dielectric overlying the silicided contact region to fill the contact opening and provide a thickness of material overlying the stop layer. An opening in the interlayer dielectric layer is formed through a portion of the thickness to expose a portion of the silicided contact region and expose a portion of the stop layer.

Abstract: A high voltage integrated circuit device includes a semiconductor substrate having a surface region with a contact region, which is coupled to a source/drain region. The device has a plasma enhanced oxide overlying the surface region, a stop layer overlying the plasma enhanced oxide, and a contact opening through a portion of the stop layer and through a portion of the plasma enhanced oxide layer. The contact opening exposes a portion of the contact region without damaging it. The device has a silicide layer overlying the contact region to form a silicided contact region and an interlayer dielectric overlying the silicided contact region to fill the contact opening and provide a thickness of material overlying the stop layer. An opening in the interlayer dielectric layer is formed through a portion of the thickness to expose a portion of the silicided contact region and expose a portion of the stop layer.

Abstract: A method for forming a shallow trench isolation structure, comprising the steps of: sequentially forming a pad oxide layer and an etch barrier layer on a semiconductor substrate, and sequentially defining the etch barrier layer, the pad oxide layer, and the substrate to form a trench; forming a liner oxide layer on the inner surface of the trench; forming a isolation oxide layer which fills up the trench and covers the sidewall of the pad oxide layer and the etch barrier layer; planarizing the isolation oxide layer until the etch barrier layer has been exposed; sequentially removing the etch barrier layer and the pad oxide layer on the substrate; forming a spin-on-glass layer on the substrate and the isolation oxide layer such that the recess on the sidewall of the trench is filled with the spin-on-glass; performing the process of removing the spin-on-glass layer until both of the substrate and the isolation oxide layer have been exposed.