Abstract: In certain aspects, a semiconductor die includes a power rail, a first gate, and a second gate. The semiconductor die also includes a first gate contact electrically coupled to the first gate, wherein the first gate contact is formed from a first middle of line (MOL) metal layer, and a second gate contact electrically coupled to the second gate, wherein the second gate contact is formed from the first MOL metal layer. The semiconductor die further includes an interconnect formed from a second MOL metal layer, wherein the interconnect is electrically coupled to the first and second gate contacts, and at least a portion of the interconnect is underneath the power rail.

Abstract: A signal interconnect includes a transmission line, a termination circuit coupled to the transmission line, and a high pass filter circuit coupled in series along the transmission line. The high pass filter circuit includes a first resistive circuit and a first capacitive circuit coupled in parallel. The first resistive circuit has a resistance based on a difference between a resistance of the transmission line at a high frequency and a resistance of the transmission line at a low frequency.

Abstract: In certain aspects, a semiconductor die includes a power rail, a first gate, and a second gate. The semiconductor die also includes a first gate contact electrically coupled to the first gate, wherein the first gate contact is formed from a first middle of line (MOL) metal layer, and a second gate contact electrically coupled to the second gate, wherein the second gate contact is formed from the first MOL metal layer. The semiconductor die further includes an interconnect formed from a second MOL metal layer, wherein the interconnect is electrically coupled to the first and second gate contacts, and at least a portion of the interconnect is underneath the power rail.

Abstract: Methods and an apparatus related to generating parameters and guidelines used in the manufacture of semiconductor IC devices are described. A method includes measuring a first oscillating signal produced by a first ring oscillator that includes a first interconnect provided in a first interconnect layer of an IC, selecting a first mode of operation for a second ring oscillator circuit that includes a second interconnect disposed in alignment with the first interconnect, selecting a second mode of operation for the second ring oscillator circuit, and determining one or more characteristics of the first interconnect based on a difference in frequency of the first oscillating signal produced when the second ring oscillator circuit is operated in the first mode and frequency of the first oscillating signal when the second ring oscillator circuit is operated in the second mode.

Abstract: A MOS device includes a first latch configured with one latch feedback F and configured to receive a latch input I and a latch clock C. The first latch is configured to output Q, where the output Q is a function of CF, IF, and IC, and the latch feedback F is a function of the output Q. The first latch may include a first set of transistors stacked in series in which the first set of transistors includes at least five transistors. The MOS device may further include a second latch coupled to the first latch. The second latch may be configured as a latch in a scan mode and as a pulse latch in a functional mode. The first latch may operate as a master latch and the second latch may operate as a slave latch during the scan mode.

Abstract: A pulse generator includes a latch module for storing first/second states, a pulse clock module for generating a clock pulse, and a delay module for delaying the clock pulse at a second latch-module input. The latch module has a first latch-module input coupled to a clock, the second latch-module input, and a latch-module output. The pulse clock module has a first pulse-clock-module input coupled to the clock, a second pulse-clock-module input coupled to the latch-module output, and a pulse-clock-module output. The delay module is coupled between the latch-module output and second pulse-clock-module input or between the pulse-clock-module output and second latch-module input. The delay module provides functionally I1IA at a delay module output, where I1 is a function of I and IA is a function of IN0 and B0, and where I is a delay module input, B0 is a first input bit, and IN0 is a first net input.

Abstract: A signal interconnect includes a transmission line, a termination circuit coupled to the transmission line, and a high pass filter circuit coupled in series along the transmission line. The high pass filter circuit includes a first resistive circuit and a first capacitive circuit coupled in parallel. The first resistive circuit has a resistance based on a difference between a resistance of the transmission line at a high frequency and a resistance of the transmission line at a low frequency.

Abstract: A MOS device includes a first latch configured with one latch feedback F and configured to receive a latch input I and a latch clock C. The first latch is configured to output Q, where the output Q is a function of CF, IF, and IC, and the latch feedback F is a function of the output Q. The first latch may include a first set of transistors stacked in series in which the first set of transistors includes at least five transistors. The MOS device may further include a second latch coupled to the first latch. The second latch may be configured as a latch in a scan mode and as a pulse latch in a functional mode. The first latch may operate as a master latch and the second latch may operate as a slave latch during the scan mode.

Abstract: A pulse generator includes a latch module for storing first/second states, a pulse clock module for generating a clock pulse, and a delay module for delaying the clock pulse at a second latch-module input. The latch module has a first latch-module input coupled to a clock, the second latch-module input, and a latch-module output. The pulse clock module has a first pulse-clock-module input coupled to the clock, a second pulse-clock-module input coupled to the latch-module output, and a pulse-clock-module output. The delay module is coupled between the latch-module output and second pulse-clock-module input or between the pulse-clock-module output and second latch-module input. The delay module provides functionally I1IA at a delay module output, where I1 is a function of I and IA is a function of IN0 and B0, and where I is a delay module input, B0 is a first input bit, and IN0 is a first net input.

Abstract: Methods and an apparatus related to generating parameters and guidelines used in the manufacture of semiconductor IC devices are described. A method includes measuring a first oscillating signal produced by a first ring oscillator that includes a first interconnect provided in a first interconnect layer of an IC, selecting a first mode of operation for a second ring oscillator circuit that includes a second interconnect disposed in alignment with the first interconnect, selecting a second mode of operation for the second ring oscillator circuit, and determining one or more characteristics of the first interconnect based on a difference in frequency of the first oscillating signal produced when the second ring oscillator circuit is operated in the first mode and frequency of the first oscillating signal when the second ring oscillator circuit is operated in the second mode.

Abstract: A method operational within a simulation environment is provided for estimating or predicting jitter. At least two step functions are defined to approximate a worst-case jitter condition for a simulated electrical interconnect or a simulated electrical path. Each of the at least two step functions is sequentially used as input signals to the simulated electrical interconnect or path to obtain at least two corresponding step function responses. Jitter for the simulated electrical interconnect or path is predicted based on the at least two step function responses.