Patents by Inventor Zhenjun Hu

Zhenjun Hu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7114011
    Abstract: A multiprocessor-scalable streaming data server arrangement in a multiprocessor data server having N processors, N being an integer greater than or equal to 2, includes implementing N NICs (Network Interface Cards), a first one of the N NICs being dedicated to receiving an incoming data stream. An interrupt from the first one of the N NICs is bound to a first one of the N processors and an interrupt for an nth NIC is bound to an nth processor, 0<n<=N. A DPC (Deferred Procedure Call) for the nth NIC is bound to the nth processor. M client connections may be tightly coupled to the nth processor via the nth NIC, M being a positive integer. P server threads may be bound to specific ones of a second through N processors. L1 (Level 1) and L2 (Level 2) caches may be defined for each of the N processors, instructions and temporal data being stored in L2 caches of the N processors and non-temporal data being stored in L1 caches of the N processors, bypassing the L2 caches.
    Type: Grant
    Filed: August 30, 2001
    Date of Patent: September 26, 2006
    Assignee: Intel Corporation
    Inventors: Deep K. Buch, Zhenjun Hu, Neil Schaper, David Zhao, Vladimir M. Pentkovski
  • Publication number: 20030046511
    Abstract: A multiprocessor-scalable streaming data server arrangement in a multiprocessor data server having N processors, N being an integer greater than or equal to 2, includes implementing N NICs (Network Interface Cards), a first one of the N NICs being dedicated to receiving an incoming data stream. An interrupt from the first one of the N NICs is bound to a first one of the N processors and an interrupt for an nth NIC is bound to an nth processor, 0<n<=N. A DPC (Deferred Procedure Call) for the nth NIC is bound to the nth processor. M client connections may be tightly coupled to the nth processor via the nth NIC, M being a positive integer. P server threads may be bound to specific ones of a second through N processors. L1 (Level 1) and L2 (Level 2) caches may be defined for each of the N processors, instructions and temporal data being stored in L2 caches of the N processors and non-temporal data being stored in L1 caches of the N processors, bypassing the L2 caches.
    Type: Application
    Filed: August 30, 2001
    Publication date: March 6, 2003
    Inventors: Deep K. Buch, Zhenjun Hu, Neil Schaper, David Zhao, Vladimir M. Pentkovski