Patents by Inventor Zhenlei Z. SHEN

Zhenlei Z. SHEN has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Physical secure erase of solid state drives
    Patent number: 10839914
    Abstract: Embodiments of the present disclosure relate to physical secure erase (PSE) of solid state drives (SSDs). One embodiment of a method of PSE of a SSD includes receiving a PSE command, erasing the memory cells of the blocks, programming the memory cells, and programming the select gates to a portion of the blocks. One embodiment of a SSD includes a controller and a plurality of blocks having a plurality of NAND strings. Each NAND string includes connected in series a select gate drain, memory cells, and a select gate source. The SSD includes a memory erasing instruction that cause the controller to erase the memory cells of the block, program the memory cells, and increase the threshold voltage to the select gate drain and/or the select gate source of some of the NAND strings from the blocks.
    Type: Grant
    Filed: April 23, 2019
    Date of Patent: November 17, 2020
    Assignee: WESTERN DIGITAL TECHNOLOGIES, Inc.
    Inventors: Zhenlei Z. Shen, Nian Niles Yang, Gautham Reddy
  • PHYSICAL SECURE ERASE OF SOLID STATE DRIVES
    Publication number: 20190252025
    Abstract: Embodiments of the present disclosure relate to physical secure erase (PSE) of solid state drives (SSDs). One embodiment of a method of PSE of a SSD includes receiving a PSE command, erasing the memory cells of the blocks, programming the memory cells, and programming the select gates to a portion of the blocks. One embodiment of a SSD includes a controller and a plurality of blocks having a plurality of NAND strings. Each NAND string includes connected in series a select gate drain, memory cells, and a select gate source. The SSD includes a memory erasing instruction that cause the controller to erase the memory cells of the block, program the memory cells, and increase the threshold voltage to the select gate drain and/or the select gate source of some of the NAND strings from the blocks.
    Type: Application
    Filed: April 23, 2019
    Publication date: August 15, 2019
    Inventors: Zhenlei Z. Shen, Nian Niles Yang, Gautham Reddy
  • Physical secure erase of solid state drives
    Patent number: 10297324
    Abstract: Embodiments of the present disclosure relate to physical secure erase (PSE) of solid state drives (SSDs). One embodiment of a method of PSE of a SSD includes receiving a PSE command, erasing the memory cells of the blocks, programming the memory cells, and programming the select gates to a portion of the blocks. One embodiment of a SSD includes a controller and a plurality of blocks having a plurality of NAND strings. Each NAND string includes connected in series a select gate drain, memory cells, and a select gate source. The SSD includes a memory erasing instruction that cause the controller to erase the memory cells of the block, program the memory cells, and increase the threshold voltage to the select gate drain and/or the select gate source of some of the NAND strings from the blocks.
    Type: Grant
    Filed: May 25, 2017
    Date of Patent: May 21, 2019
    Assignee: Western Digital Technologies, Inc.
    Inventors: Zhenlei Z. Shen, Nian Niles Yang, Gautham Reddy
  • PHYSICAL SECURE ERASE OF SOLID STATE DRIVES
    Publication number: 20180342301
    Abstract: Embodiments of the present disclosure relate to physical secure erase (PSE) of solid state drives (SSDs). One embodiment of a method of PSE of a SSD includes receiving a PSE command, erasing the memory cells of the blocks, programming the memory cells, and programming the select gates to a portion of the blocks. One embodiment of a SSD includes a controller and a plurality of blocks having a plurality of NAND strings. Each NAND string includes connected in series a select gate drain, memory cells, and a select gate source. The SSD includes a memory erasing instruction that cause the controller to erase the memory cells of the block, program the memory cells, and increase the threshold voltage to the select gate drain and/or the select gate source of some of the NAND strings from the blocks.
    Type: Application
    Filed: May 25, 2017
    Publication date: November 29, 2018
    Inventors: Zhenlei Z. SHEN, Nian Niles YANG, Gautham REDDY