Abstract: An apparatus for monitoring a trench profile of a substrate includes a radiation-emitting unit for irradiating the substrate with infrared radiation. The intensity and/or polarization state of the infrared radiation reflected from the substrate is measured at a multitude of measuring frequencies. An analyzing unit determines the respective reflectance and relative phase change and/or relative amplitude change in relation to the respective measuring frequency. In addition, a reflectance spectrum, a relative phase change spectrum and/or a relative amplitude change spectrum may be obtained. By performing a Fourier transformation of the respective spectrum, a secondary Fourier spectrum is obtained. The secondary Fourier spectrum plots a virtual amplitude against corresponding values of a frequency periodicity that correspond to a substrate depth. Peaks of the virtual amplitude may indicate reflective planes within the substrate at respective depths.

Abstract: An apparatus for monitoring a trench profile of a substrate includes a radiation-emitting unit for irradiating the substrate with infrared radiation. The intensity and/or polarization state of the infrared radiation reflected from the substrate is measured at a multitude of measuring frequencies. An analyzing unit determines the respective reflectance and relative phase change and/or relative amplitude change in relation to the respective measuring frequency. In addition, a reflectance spectrum, a relative phase change spectrum and/or a relative amplitude change spectrum may be obtained. By performing a Fourier transformation of the respective spectrum, a secondary Fourier spectrum is obtained. The secondary Fourier spectrum plots a virtual amplitude against corresponding values of a frequency periodicity that correspond to a substrate depth. Peaks of the virtual amplitude may indicate reflective planes within the substrate at respective depths.

Abstract: A method of fabricating a stacked gate dielectric layer. First, a semiconductor substrate having a native oxide thereon is provided. Next, a first gas containing hydrogen is introduced on the semiconductor substrate. A nitride is deposited on the native oxide. A second gas containing nitrous oxide is introduced on the semiconductor substrate. A third gas containing nitrogen oxide is introduced on the semiconductor substrate. Finally, an annealing treatment is performed.

Abstract: A method of etching a metal line. A substrate with a metal layer to be etched is provided, on which an amorphous carbon doped layer is formed over the metal layer by plasma enhanced chemical vapor deposition (PECVD). A resist layer is formed over the amorphous carbon doped layer, and the resist layer is patterned to define a resist mask. The amorphous carbon doped layer is etched to define a hardmask, the resist mask is stripped, and the metal layer not covered by the hardmask is etched to form a metal line for forming an interconnect.

Abstract: A method of fabricating a well-filled STI Structure in a semiconductor substrate. A trench is formed in the semiconductor substrate. A liner oxide and a liner nitride are formed on the bottom and sidewall of the trench subsequently. A HDP oxide layer is deposited in the trench conformally to fill a portion of the trench. A layer of poly-silicon is deposited over the HDP oxide layer conformally. The semiconductor substrate is subjected to a thermal treatment to oxidize the poly-silicon. The surface of the semiconductor substrate is planarized to form a shallow trench isolation structure. The trench is well filled by the oxidized poly-silicon and the HDP oxide without voids and seams.

Abstract: A method of etching a low-k dielectric layer. A substrate having a low-k dielectric layer to be etched, on which an amorphous carbon doped layer is formed over the low-k dielectric layer by plasma enhanced chemical vapor deposition (PECVD), a resist layer is formed over the amorphous carbon doped layer , and the resist layer is patterned to define a first opening thereby forming a resist mask. The amorphous carbon doped layer is etched to define a second opening, thereby forming a hardmask, the resist mask is stripped, and the low-k dielectric layer not covered by the hardmask is etched to form a third opening as a trench or via.