Abstract: Aspects of the present disclosure configure a system component, such as memory sub-system controller, to perform empty page scan operations. The controller selects a portion of the set of memory components that is empty and ready to be programmed. The controller reads one or more signals from the selected portion of the set of memory components. The controller generates an error count value representing whether the portion of the set of memory components is valid for programming based on a result of reading the one or more signals from the selected portion. The controller updates a scan frequency for performing the empty page scan operations for the portion of the set of memory components based on the error count value.

Abstract: A controller of a memory device may identify a plurality of word line groups, included in a block of a memory of the memory device, that include erased pages of the block. The controller may identify a subset of word line groups, of the plurality of word line groups, for a NAND detect empty page (NDEP) scan operation. The controller may perform, based on identifying the subset of word line groups, the NDEP scan operation for the subset of word line groups. A voltage threshold for the NDEP scan may be based on an offset voltage that can be adaptive based on parameters such as quantity of program-erase cycles, memory cell type, and/or operating temperature, among other examples.

Abstract: A power supply circuit and an apparatus includes: a first switching transistor, a second switching transistor, a third switching transistor, a fourth switching transistor, a first capacitor, and a second capacitor. In this power supply circuit, one terminal of the first capacitor is connected to one terminal of the second capacitor, the other terminal of the first capacitor is separately connected to a first electrode of the first switching transistor and a first electrode of the second switching transistor, a second electrode of the first switching transistor is connected to a second electrode of the third switching transistor, a second electrode of the second switching transistor is connected to a second electrode of the fourth switching transistor, a third electrode of the first switching transistor is connected to an output node, and a third electrode of the second switching transistor is grounded.

Abstract: A power supply circuit and an apparatus includes: a first switching transistor, a second switching transistor, a third switching transistor, a fourth switching transistor, a first capacitor, and a second capacitor. In this power supply circuit, one terminal of the first capacitor is connected to one terminal of the second capacitor, the other terminal of the first capacitor is separately connected to a first electrode of the first switching transistor and a first electrode of the second switching transistor, a second electrode of the first switching transistor is connected to a second electrode of the third switching transistor, a second electrode of the second switching transistor is connected to a second electrode of the fourth switching transistor, a third electrode of the first switching transistor is connected to an output node, and a third electrode of the second switching transistor is grounded.

Abstract: Disclosed are a telescopic transmission cable device and a mobile terminal.

Abstract: Disclosed are a telescopic transmission cable device and a mobile terminal.

Abstract: A dual-rotor engine comprises a cylinder assembly, a transmission output mechanism, a rotor control mechanism and a lubrication system. The cylinder assembly comprises a tubular cylinder (6) and two rotors (1a, 1b). Each of the rotors (1a, 1b) comprises an inner cylindrical cylinder (99a, 99b), a rotor journal (20a, 20b) integrated with the inner cylindrical cylinder (99a, 99b) and two sector pistons (17a, 17b) symmetrically secured to the inner cylindrical cylinder (99a, 99b); four sector pistons (17a, 17b) of two rotors (1a, 1b) are arranged crosswise to each other, and two adjacent sector pistons (17a, 17b) form a combustion chamber. The transmission output mechanism comprises two rotor gears (2a, 2b) and two driving gears (3a, 3b) which engaged with each other respectively.

Abstract: A battery management system includes a monitoring circuit and a charger. The monitoring circuit is operable for monitoring a battery pack that includes a plurality of cells, and for checking an unbalanced condition of the battery pack in each cycle of a plurality of cycles. The charger is operable for controlling a charging current to the battery pack and for receiving monitoring information from the monitoring circuit, and for adjusting the charging current from a first level in a previous cycle to a second level that is lower than the first level in response to a detection of the unbalanced condition in a current cycle.

Abstract: A dual-rotor engine comprises a cylinder assembly, a transmission output mechanism, a rotor control mechanism and a lubrication system. The cylinder assembly comprises a tubular cylinder (6) and two rotors (1a, 1b). Each of the rotors (1a, 1b) comprises an inner cylindrical cylinder (99a, 99b), a rotor journal (20a, 20b) integrated with the inner cylindrical cylinder (99a, 99b) and two sector pistons (17a, 17b) symmetrically secured to the inner cylindrical cylinder (99a, 99b); four sector pistons (17a, 17b) of two rotors (1a, 1b) are arranged crosswise to each other, and two adjacent sector pistons (17a, 17b) form a combustion chamber. The transmission output mechanism comprises two rotor gears (2a, 2b) and two driving gears (3a, 3b) which engaged with each other respectively.

Abstract: A battery management system includes a monitoring circuit and a charger. The monitoring circuit is operable for monitoring a battery pack that includes a plurality of cells, and for checking an unbalanced condition of the battery pack in each cycle of a plurality of cycles. The charger is operable for controlling a charging current to the battery pack and for receiving monitoring information from the monitoring circuit, and for adjusting the charging current from a first level in a previous cycle to a second level that is lower than the first level in response to a detection of the unbalanced condition in a current cycle.