Abstract: A shift register, a gate driving circuit, a display panel and a driving method. The shift register includes: an input and set circuit, connected with a pull-up node; a storage circuit, connected with the pull-up node and an output end respectively; an output circuit, configured to provide a second clock signal to the output end when a voltage of the pull-up node satisfies an output condition; and a first pull-down circuit, configured to provide a first power voltage to the output end when a first pull-down condition is satisfied. The input and set circuit is further configured to: in a set stage of forward scanning or an input stage of reverse scanning, receive a third clock signal and a second input signal, and in response to the third clock signal, write a voltage of the second input signal into the pull-up node.