Abstract: Provided is a semiconductor power device. The semiconductor power device includes a semiconductor substrate and p-type body regions disposed in the semiconductor substrate. The p-type body regions are in contact with a source metal layer. The semiconductor substrate includes at least one first region, and a region of the semiconductor substrate outside the at least one first region is a second region. A p-type body region of p-type body regions in the first region is provided with a first p-type body region contact region, and the source metal layer is in contact with the first p-type body region contact region to form an ohmic contact. Each of p-type body regions in the second region forms no ohmic contact with the source metal layer.

Abstract: A method for manufacturing a semiconductor power device includes forming a first recess in an n-type substrate and forming, in the first recess, a field oxide layer and a shielded gate; etching the field oxide layer in a self-aligned manner by taking the n-type substrate and the shielded gate as self-aligned boundaries, to etch away the field oxide layer in an upper portion of the first recess and to form a second recess in the upper portion of the first recess and between the shielded gate and the n-type substrate; forming an insulating dielectric layer covering sidewalls of a second recess and the bottom of the second recess and not filling the second recess; forming a layer of photoresist filling the remaining second recess; and performing photolithography, to expose the first insulating dielectric layer located in the second recess and on sides close to an n-type substrate, and etching away the first insulating dielectric layer located in the second recess and on sides close to the n-type substrate.

Abstract: A manufacturing method of a semiconductor power device includes the following steps: An n-type substrate is etched in a self-aligning manner using a first insulating layer, a second insulating layer, and a third insulating layer as a mask to form a second groove in the n-type substrate. A fourth insulating layer and a gate are formed in the second groove.

Abstract: A gate trench and a source trench are formed simultaneously in the same etching process, a p-type semiconductor layer and a p-type doped region can be contacted in a self-aligned manner in the source trench, and the process is simple. A first insulating layer and a first gate are formed in a lower part of the gate trench, and a second insulating layer and a second gate are formed in an upper part of the gate trench so that the thick first insulating layer can protect the second gate from being easily broken down, the first gate can increase an electric field near a bottom of the gate trench, and thus a voltage withstand level of the semiconductor device can be improved. A bottom of the source trench can penetrate deep into a second n-type semiconductor layer .

Abstract: The present application belongs to the technical field of semiconductor power devices and provides a semiconductor power device. The semiconductor power device includes an n-shaped substrate, an n-shaped epitaxial layer positioned on the n-shaped substrate, and at least three grooves recessed inside the n-shaped epitaxial layer, where a portion of the n-shaped epitaxial layer between two adjacent grooves of the at least three grooves is a mesa structure, an upper part of the mesa structure is provided with a p-shaped body region, and an n-shaped source region is provided inside the p-shaped body region. The mesa structure includes at least one mesa structure with a lower width being a first width and at least one mesa structure with a lower width being a second width, and the second width is greater than the first width.

Abstract: Disclosed is a method for manufacturing a semiconductor super-junction device. The method includes: a p-type column is formed through an epitaxial process, and then a gate is formed in a self-alignment manner.

Abstract: Disclosed is a method for manufacturing a semiconductor super-junction device. The method includes: a p-type column is formed through an epitaxial process, and then a gate is formed in a self-alignment manner.

Abstract: A method of screening compounds for their ability of inhibiting ligand-induced co-stimulatory receptor internalisation pathways in immune competent human cells is described. The immune competent human cells are incubated at conditions capable of inducing co-stimulatory receptor internalisation in the presence of at least one test compound and the suppression of the ligand-induced co-stimulatory receptor internalisation is determined. There is also described a kit for use in such a method, as well as an immunoregulatory drug capable of blocking down-modulation of a ligand-induced receptor.