Patents by Inventor Zhenyn Lawrence Liu

Zhenyn Lawrence Liu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6751315
    Abstract: A high bandwidth telephone line transceiver for connecting telecommunications equipment to a telephone line provides a pair of isolation capacitors connected to the telephone line to transmit the telephone signals across the requisite electrical isolation barrier. The capacitors are connected to a user-side hybrid circuit that provides a line impedance match for the telephone circuit, and converts the two wire connection to the capacitors to a 4 wire circuit for separate transmit and receive signal paths. The receive signal path extends through a signal op amp to a high pass filter that transmits the DSL download bandwidth and rejects the upload bandwidth and voice spectrum. The received signal is then fed to an analog/digital converter, and the digitized signal is connected to a DSP. The DSP is connected to a data handling device via a USB port, a PCI interface, or the like. The transmit signal path extends from the DSP circuit to a transmit path digital/analog converter.
    Type: Grant
    Filed: October 18, 1999
    Date of Patent: June 15, 2004
    Assignee: Silicon Labs Isolation, Inc.
    Inventors: Zhenyn Lawrence Liu, Gerald J. Yurgelites
  • Patent number: 6212060
    Abstract: A multi-capacitor device having a plurality of capacitors in a single circuit package is formed of a plurality of layers of dielectric material, preferably the same type of material that is commonly used to fabricate circuit boards. The plurality of layers are disposed in a vertically stacked relationship. Each capacitor is formed of first and second pluralities of planar electrodes formed on alternating layers of the stack. The first plurality of electrodes is disposed in a first vertically stacked array, and the second plurality of electrodes is disposed in a second vertically stacked array. Each vertical electrode array is provided with a via hole extending through all of its layers to connect all of the respective electrode array in parallel. At the upper surface of the assembly, each via hole is connected to a solder pad and disposed to be soldered to a connection point on a printed circuit board or the like.
    Type: Grant
    Filed: March 31, 1999
    Date of Patent: April 3, 2001
    Assignee: Krypton Isolation, Inc.
    Inventor: Zhenyn Lawrence Liu