Abstract: In accordance with an embodiment, a communication method applied to a first node includes: receiving first information from a second node, wherein the first information comprises an available space size in a first buffer space of the second node, the first buffer space is for buffering a data packet that is to be transmitted through a first path, the first path is a primary path for transmitting the data packet, and the second node is a next-hop node of the first node on the primary path; and in response to the available space size in the first buffer space being less than or equal to a first threshold, determining to transmit the data packet through a third node, wherein the third node is a next-hop node of the first node on a backup path for transmitting the data packet.

Abstract: The present disclosure relates to methods applied to an integrated access and backhaul (IAB) node. An example method includes receiving configuration information for setup of a distributed unit (DU) part of the IAB node and determining, based on a manner of receiving the configuration information, that a master node of the IAB node or a secondary node of the IAB node is a donor node of the IAB node.

Abstract: Circuitry comprises memory access control circuitry responsive to initiation of a memory access transaction relating to a given memory address, the memory access transaction being initiated in an access mode selected from at least a higher access mode and a lower access mode, the higher access mode having a higher access level than the lower access mode such that memory access transactions in the lower access mode are inhibited from accessing at least some processing resources associated with memory access transactions in the higher access mode, the memory access control circuitry comprising: circuitry to access permission data associated with candidate memory addresses to be accessed; detector circuitry to detect, for a memory access transaction initiated in the lower access mode, whether the permission data associated with the given memory address indicates an upgraded access mode; and transaction modifier circuitry to associate with the memory access transaction an indication that the memory access transac

Abstract: Circuitry comprises memory access control circuitry responsive to initiation of a memory access transaction relating to a given memory address, the memory access transaction being initiated in an access mode selected from at least a higher access mode and a lower access mode, the higher access mode having a higher access level than the lower access mode such that memory access transactions in the lower access mode are inhibited from accessing at least some processing resources associated with memory access transactions in the higher access mode, the memory access control circuitry comprising: circuitry to access permission data associated with candidate memory addresses to be accessed; detector circuitry to detect, for a memory access transaction initiated in the lower access mode, whether the permission data associated with the given memory address indicates an upgraded access mode; and transaction modifier circuitry to associate with the memory access transaction an indication that the memory access transac