Patents by Inventor ZHIBIAO ZHOU
ZHIBIAO ZHOU has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11923373Abstract: A semiconductor structure includes a semiconductor on insulator (SOI) substrate, a first electrically conductive structure, and a second electrically conductive structure. The SOI substrate includes a base substrate, a buried insulation layer disposed on the base substrate, a semiconductor layer disposed on the buried insulation layer, and a trap rich layer disposed between the buried insulation layer and the base substrate. At least a part of the first electrically conductive structure and at least a part of the second electrically conductive structure are disposed in the trap rich layer. A part of the trap rich layer is disposed between the first electrically conductive structure and the second electrically conductive structure. The first electrically conductive structure, the second electrically conductive structure, and the trap rich layer disposed between the first electrically conductive structure and the second electrically conductive structure are at least a portion of an anti-fuse structure.Type: GrantFiled: October 14, 2021Date of Patent: March 5, 2024Assignee: UNITED MICROELECTRONICS CORP.Inventors: Bo Tao, Li Wang, Ching-Yang Wen, Purakh Raj Verma, Zhibiao Zhou, Dong Yin, Gang Ren, Jian Xie
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Publication number: 20240021593Abstract: A light-emitting diode (LED) structure is provided in the present invention, including a substrate, a dielectric layer on the substrate, metal interconnects in the dielectric layer, LED dies on the dielectric layer, wherein each LED die is provided with a front side and a back side, the back side is bonded with the dielectric layer, and the cathode and anode are on the front side of LED die, and bonding lines connecting the cathode and anode on the front side of LED die to the metal interconnects respectively.Type: ApplicationFiled: August 18, 2022Publication date: January 18, 2024Applicant: UNITED MICROELECTRONICS CORP.Inventor: ZHIBIAO ZHOU
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Publication number: 20230400692Abstract: A method of manufacturing a layout structure of Micro LED for augmented reality and mixed reality is provided in the present invention, including steps of providing a substrate with multiple display units arranged thereon to form an unit array and includes an edge region and a transparent region surrounded by the edge region, forming pixel driver circuits and a first transparent layer on the edge region, setting multiple Micro LEDs on the first transparent layer of edge regions, forming a second transparent layer on the Micro LEDs and the first transparent layer, thinning and removing the substrate on the transparent region to expose the first transparent layer, and forming a protection layer on back sides of the substrate and the exposed first transparent layer.Type: ApplicationFiled: August 21, 2023Publication date: December 14, 2023Applicant: UNITED MICROELECTRONICS CORP.Inventor: ZHIBIAO ZHOU
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Publication number: 20230335629Abstract: A high electron mobility transistor (HEMT) includes a first doped layer disposed in a substrate, a mesa isolation disposed on the substrate, a gate electrode disposed on the mesa isolation, a source electrode and a drain electrode disposed adjacent to two sides of the gate electrode, a passivation layer disposed on the mesa isolation and around the source electrode and the drain electrode, a first metal line connecting the source electrode and the first doped layer, and a second metal line connecting the drain electrode and the first doped layer.Type: ApplicationFiled: May 17, 2022Publication date: October 19, 2023Applicant: UNITED MICROELECTRONICS CORP.Inventor: ZHIBIAO ZHOU
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Patent number: 11774766Abstract: A layout of Micro LED for augmented reality (AR) and mixed reality (MR) is provided in the present invention, including multiple display cells arranging into a cell array, multiple micro LEDs set on the edge region of each display cell and exposing the transparent region surrounded by the edge region, and pixel driver circuits set on the edge region right under the Micro LEDs.Type: GrantFiled: December 15, 2022Date of Patent: October 3, 2023Assignee: UNITED MICROELECTRONICS CORP.Inventor: Zhibiao Zhou
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Publication number: 20230110502Abstract: A layout of Micro LED for augmented reality (AR) and mixed reality (MR) is provided in the present invention, including multiple display cells arranging into a cell array, multiple micro LEDs set on the edge region of each display cell and exposing the transparent region surrounded by the edge region, and pixel driver circuits set on the edge region right under the Micro LEDs.Type: ApplicationFiled: December 15, 2022Publication date: April 13, 2023Applicant: UNITED MICROELECTRONICS CORP.Inventor: ZHIBIAO ZHOU
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Publication number: 20230082878Abstract: A semiconductor structure includes a semiconductor on insulator (SOI) substrate, a first electrically conductive structure, and a second electrically conductive structure. The SOI substrate includes a base substrate, a buried insulation layer disposed on the base substrate, a semiconductor layer disposed on the buried insulation layer, and a trap rich layer disposed between the buried insulation layer and the base substrate. At least a part of the first electrically conductive structure and at least a part of the second electrically conductive structure are disposed in the trap rich layer. A part of the trap rich layer is disposed between the first electrically conductive structure and the second electrically conductive structure. The first electrically conductive structure, the second electrically conductive structure, and the trap rich layer disposed between the first electrically conductive structure and the second electrically conductive structure are at least a portion of an anti-fuse structure.Type: ApplicationFiled: October 14, 2021Publication date: March 16, 2023Applicant: UNITED MICROELECTRONICS CORP.Inventors: BO TAO, Li Wang, Ching-Yang Wen, Purakh Raj Verma, ZHIBIAO ZHOU, DONG YIN, Gang Ren, Jian Xie
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Patent number: 11561403Abstract: A layout of Micro LED for augmented reality (AR) and mixed reality (MR) is provided in the present invention, including multiple display cells arranging into a cell array, multiple micro LEDs set on the edge region of each display cell and exposing the transparent region surrounded by the edge region, and pixel driver circuits set on the edge region right under the Micro LEDs.Type: GrantFiled: June 23, 2021Date of Patent: January 24, 2023Assignee: UNITED MICROELECTRONICS CORP.Inventor: Zhibiao Zhou
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Publication number: 20220373801Abstract: A layout of Micro LED for augmented reality (AR) and mixed reality (MR) is provided in the present invention, including multiple display cells arranging into a cell array, multiple micro LEDs set on the edge region of each display cell and exposing the transparent region surrounded by the edge region, and pixel driver circuits set on the edge region right under the Micro LEDs.Type: ApplicationFiled: June 23, 2021Publication date: November 24, 2022Applicant: UNITED MICROELECTRONICS CORP.Inventor: ZHIBIAO ZHOU
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Patent number: 11011649Abstract: An oxide semiconductor device and a method for manufacturing the same are provided in the present invention. The oxide semiconductor device includes a back gate, an oxide semiconductor film, a pair of source and drain electrodes, a gate insulating film, a gate electrode on the oxide semiconductor film with the gate insulating film therebetween, an insulating layer covering only over the gate electrode and the pair of source and drain electrodes, and a top blocking film over the insulating layer.Type: GrantFiled: July 5, 2018Date of Patent: May 18, 2021Assignee: UNITED MICROELECTRONICS CORP.Inventors: Zhibiao Zhou, Shao-Hui Wu, Chen-Bin Lin, Ding-Lung Chen, Chi-Fa Ku
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Publication number: 20200294933Abstract: A semiconductor structure is provided, the semiconductor structure includes a front oxide layer on a backside oxide layer, a front electronic component in the front oxide layer, a backside electronic component in the backside oxide layer, and a shield structure disposed between the front oxide layer and the backside oxide layer, the shield structure includes a patterned buried metal layer, two front contact structures disposed on a front surface of the patterned buried metal layer, and two back contact structures disposed on a backside of the patterned buried metal layer.Type: ApplicationFiled: March 31, 2019Publication date: September 17, 2020Inventor: ZHIBIAO ZHOU
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Patent number: 10756027Abstract: A semiconductor structure is provided, the semiconductor structure includes a front oxide layer on a backside oxide layer, a front electronic component in the front oxide layer, a backside electronic component in the backside oxide layer, and a shield structure disposed between the front oxide layer and the backside oxide layer, the shield structure includes a patterned buried metal layer, two front contact structures disposed on a front surface of the patterned buried metal layer, and two back contact structures disposed on a backside of the patterned buried metal layer.Type: GrantFiled: March 31, 2019Date of Patent: August 25, 2020Assignee: UNITED MICROELECTRONICS CORP.Inventor: Zhibiao Zhou
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Patent number: 10727234Abstract: The present invention provides a layout of a semiconductor transistor device including a first and a second active area, a first and a second gate, and a metal line. The first active and the second active area are extended along a first direction. The first gate and the second gate are extended along a second direction and crossed the first active area, to define two transistors. The two transistors are electrically connected with each other through a conductive layer. The metal line is disposed on the conductive layer and is electrically connected the two transistors respectively.Type: GrantFiled: November 27, 2016Date of Patent: July 28, 2020Assignee: UNITED MICROELECTRONICS CORP.Inventors: Zhibiao Zhou, Ding-Lung Chen, Xing Hua Zhang, Shan Liu, Runshun Wang, Chien-Fu Chen, Wei-Jen Wang, Chen-Hsien Hsu
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Patent number: 10644166Abstract: The present invention provides a method for forming a semiconductor structure, the method includes: firstly, a substrate having a recess disposed therein is provided, wherein the substrate comprises a silicon substrate, next, a first element is formed in the recess and arranged along a first direction, wherein the first element is made of an oxidation semiconductor material, afterwards, a dielectric layer is formed on the first element, and a second element is formed on dielectric layer and arranged along the first direction, wherein the second element is used as the gate structure of a transistor structure.Type: GrantFiled: September 13, 2018Date of Patent: May 5, 2020Assignee: UNITED MICROELECTRONICS CORP.Inventors: Zhibiao Zhou, Shao-Hui Wu, Chi-Fa Ku
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Patent number: 10629748Abstract: A semiconductor device includes a substrate, a source region and a drain region, a gate dielectric layer, and a ferroelectric material layer. The ferroelectric material layer overlaps with the source region and overlaps with the drain region. The substrate further comprises a channel layer. A gate electrode is disposed on the substrate. The ferroelectric material layer is disposed between the channel layer and the gate electrode.Type: GrantFiled: July 20, 2017Date of Patent: April 21, 2020Assignee: UNITED MICROELECTRONICS CORP.Inventors: Pengfei Guo, Shao-Hui Wu, Hai Biao Yao, Yu-Cheng Tung, Yuanli Ding, Zhibiao Zhou
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Patent number: 10504903Abstract: A semiconductor device includes a substrate, a semiconductor channel layer, a gate electrode, and a first memory structure. The semiconductor channel layer is disposed on the substrate. The gate electrode and the first memory structure are disposed on the semiconductor channel layer. The first memory structure includes a first bottom plate, a first top plate, and a first memory element layer. The first top plate is disposed on the first bottom plate. The first memory element layer is disposed between the first bottom plate and the first top plate. The first bottom plate contacts the semiconductor channel layer. Purposes of process simplification and/or memory density enhancement may be achieved by integrating a transistor with a memory structure.Type: GrantFiled: June 6, 2018Date of Patent: December 10, 2019Assignee: UNITED MICROELECTRONICS CORP.Inventor: Zhibiao Zhou
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Publication number: 20190363087Abstract: A semiconductor device includes a substrate, a semiconductor channel layer, a gate electrode, and a first memory structure. The semiconductor channel layer is disposed on the substrate. The gate electrode and the first memory structure are disposed on the semiconductor channel layer. The first memory structure includes a first bottom plate, a first top plate, and a first memory element layer. The first top plate is disposed on the first bottom plate. The first memory element layer is disposed between the first bottom plate and the first top plate. The first bottom plate contacts the semiconductor channel layer. Purposes of process simplification and/or memory density enhancement may be achieved by integrating a transistor with a memory structure.Type: ApplicationFiled: June 6, 2018Publication date: November 28, 2019Inventor: ZHIBIAO ZHOU
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Publication number: 20190279701Abstract: A dual mode memory system is provided in the present invention, which includes a memory cell array with a plurality of oxide-semiconductor field effect transistors, each said oxide-semiconductor field effect transistor has a ferroelectric layer in the bottom gate to modulate the bottom gate bias voltage according to the polarization voltages provided by the dual mode control unit.Type: ApplicationFiled: May 29, 2019Publication date: September 12, 2019Inventors: Yuanli Ding, ZHIBIAO ZHOU
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Patent number: 10410708Abstract: A dual mode memory system is provided in the present invention, which includes a memory cell array with a plurality of oxide-semiconductor field effect transistors, each said oxide-semiconductor field effect transistor has a ferroelectric layer in the bottom gate to modulate the bottom gate bias voltage according to the polarization voltages provided by the dual mode control unit.Type: GrantFiled: May 29, 2019Date of Patent: September 10, 2019Assignee: UNITED MICROELECTRONICS CORP.Inventors: Yuanli Ding, Zhibiao Zhou
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Patent number: 10354711Abstract: A dual mode memory system is provided in the present invention, which includes a memory cell array with a plurality of oxide-semiconductor field effect transistors, each said oxide-semiconductor field effect transistor has a ferroelectric layer in the bottom gate to modulate the bottom gate bias voltage according to the polarization voltages provided by the dual mode control unit.Type: GrantFiled: August 30, 2017Date of Patent: July 16, 2019Assignee: UNITED MICROELECTRONICS CORP.Inventors: Yuanli Ding, Zhibiao Zhou