Abstract: An energy Internet system, an energy routing conversion device, and an energy control method, relating to a field of energy information. An alternating-current (AC) side energy routing conversion device of the energy Internet system includes a plurality of first route ports, and a direct-current (DC) side energy routing conversion device includes a plurality of second route ports, where each second route port is connected to a corresponding first route port by means of a corresponding DC busbar. A plurality of energy devices are connected to a DC busbar by means of corresponding first AC/DC converters or first DC converters. The AC side energy routing conversion device and the DC side energy routing conversion device collect energy information of the energy devices and adjust energy of the energy devices on a basis of energy balance constraint conditions.

Abstract: The present disclosure relates to water heaters, in particular to a water heater with convenient-to-install decorative plate. The water heater includes top, bottom decorative plate, front plate, rear housing, further includes frame. The frame includes body, upper, lower connecting bar. The rear edge of upper connecting bar is provided with first upper flanging, rear edge of lower connecting bar is provided with first lower flanging, front edge of top decorative plate is provided with second upper flanging, front edge of bottom decorative plate is provided with second lower flanging, the first upper flanging is in lap joint with the second upper flanging, second lower flanging is in lap joint with first lower flanging. Advantages: the left, right rear part of top decorative plate each can connected upper pressing bar with one screw, top and bottom decorative plate needs two screws separately. Water heater with convenient-to-install decorative plate has few screws.

Abstract: A radiation detector (100) includes an insulating substrate (110), which includes a material that undergoes a change in an electrical property when subjected to ionizing radiation. A conductive film (112) is disposed in relation to a surface of the substrate. The conductive film (112) has a resistance that is a function of a state of the electrical property. A resistance measuring device measures resistance across the conductive film (112). The resistance measured by the resistance measuring device indicates an amount of ionizing radiation to which the substrate (110) has been subjected. In a method of determining exposure to a type of radiation, a boron nitride substrate is exposed to a radiation environment. A resistance is measured across a conductive film disposed in relation to the boron nitride substrate. Radiation exposure is calculated as a function of the resistance.

Abstract: The present disclosure provides an outdoor support-type water heater, including a gas water heater main body and a water-heater bracket. By arranging at the bottom of the gas water heater main body a bracket which includes two separate brackets that are arranged at both sides of the gas water heater main body to support the gas water heater main body, the gas water heater main body may be fixed outdoors, the user just needs to connect a fuel gas vessel carried by the user to the gas inlet to complete the supply of fuel gas, and connect an outdoor water pipe to the water inlet pipe to complete the supply of water; therefore, supply of hot water is enabled outdoors with the gas water heater and a wider application scope is enabled for the water heater.

Abstract: A radiation detector (100) includes an insulating substrate (110), which includes a material that undergoes a change in an electrical property when subjected to ionizing radiation. A conductive film (112) is disposed in relation to a surface of the substrate. The conductive film (112) has a resistance that is a function of a state of the electrical property. A resistance measuring device measures resistance across the conductive film (112). The resistance measured by the resistance measuring device indicates an amount of ionizing radiation to which the substrate (110) has been subjected. In a method of determining exposure to a type of radiation, a boron nitride substrate is exposed to a radiation environment. A resistance is measured across a conductive film disposed in relation to the boron nitride substrate. Radiation exposure is calculated as a function of the resistance.

Abstract: Devices and methods relate to inducing or promoting hemostasis. The hemostasis device may include a support layer having a first surface and an opposing second surface. The device may include a layer, the layer disposed on the first surface. The layer may include a target surface configured to contact a target site. The layer may include a monolayer of about 100% graphene or may include laser-reduced graphene oxide. The device may include a sensor configured to measure a level of hemostasis of the target site. The methods relate to a method of manufacturing a hemostatic device including a monolayer of graphene or a layer of laser-reduced graphene oxide.

Abstract: A method and apparatus for testing a scan-based 3D integrated circuit (3DIC) using time-division demultiplexing/multiplexing allowing for high-data-rate scan patterns applied at input/output pads converting into low-data-rate scan patterns applied to each embeddded module in the 3DIC. A set of 3D design guidelines is proposed to reduce the number of test times and the number of through-silicon vias (TSVs) required for both pre-bond testing and post-bond testing. The technique allows reuse of scan patterns developed for pre-bond testing of each die (layer) for post-bond testing of the whole 3DIC. It further reduces test application time without concerns for I/O pad count limit and risks for fault coverage loss.

Abstract: An apparatus and method for soft-error resilience or correction with the ability to perform a manufacturing test operation, a slow-speed snapshot operation, a slow-speed signature analysis operation, an at-speed signature analysis operation, a defect tolerance operation, or any combination of the above operations. In one embodiment, an apparatus includes a system circuit, a shadow circuit, and an output joining circuit for soft-error resilience. The output joining circuit coupled to the output terminals of the system circuit and the shadow circuit includes at least an S-element for defect tolerance. In another embodiment, an apparatus includes a system circuit, a shadow circuit, a debug circuit, and an output joining circuit for soft-error correction. The output joining circuit coupled to the output terminals of the system circuit, the shadow circuit, and the debug circuit includes at least a V-element for defect tolerance.

Abstract: A low-pin-count scan compression method and apparatus for reducing test data volume and test application time in a scan-based integrated circuit. The scan-based integrated circuit contains one or more scan chains, each scan chain comprising one or more scan cells coupled in series. The method and apparatus includes a programmable pipelined decompressor comprising one or more shift registers, a combinational logic network, and an optional scan connector. The programmable pipelined decompressor decompresses a compressed scan pattern on its compressed scan inputs and drives the generated decompressed scan pattern at the output of the programmable pipelined decompressor to the scan data inputs of the scan-based integrated circuit. Any input constraints imposed by said_combinational logic network are incorporated into an automatic test pattern generation (ATPG) program for generating the compressed scan pattern for one or more selected faults in one-step.

Abstract: A low-pin-count scan compression method and apparatus for reducing test data volume and test application time in a scan-based integrated circuit. The scan-based integrated circuit contains one or more scan chains, each scan chain comprising one or more scan cells coupled in series. The method and apparatus includes a programmable pipelined decompressor comprising one or more shift registers, a combinational logic network, and an optional scan connector. The programmable pipelined decompressor decompresses a compressed scan pattern on its compressed scan inputs and drives the generated decompressed scan pattern at the output of the programmable pipelined decompressor to the scan data inputs of the scan-based integrated circuit. Any input constraints imposed by said combinational logic network are incorporated into an automatic test pattern generation (ATPG) program for generating the compressed scan pattern for one or more selected faults in one-step.

Abstract: A method for performing robust scan synthesis for soft-error protection on a design for generating a robust scan design in a system is modeled selectively at a register-transfer level (RTL) or a gate level; the design includes at least a sequential element or a scan cell for mapping to a robust scan cell of a select robust scan cell type. The method comprises performing a scan replacement and a scan stitching on the design database based on a given control information file for synthesizing the robust scan cell on the design database; and generating the synthesized robust scan design at a pre-determined RTL or a pre-determined gate level.

Abstract: A method and apparatus for testing a scan-based 3D integrated circuit (3DIC) using time-division demultiplexing/multiplexing allowing for high-data-rate scan patterns applied at input/output pads converting into low-data-rate scan patterns applied to each embeddded module in the 3DIC. A set of 3D design guidelines is proposed to reduce the number of test times and the number of through-silicon vias (TSVs) required for both pre-bond testing and post-bond testing. The technique allows reuse of scan patterns developed for pre-bond testing of each die (layer) for post-bond testing of the whole 3DIC. It further reduces test application time without concerns for I/O pad count limit and risks for fault coverage loss.

Abstract: A method for performing robust scan synthesis for soft-error protection on a design for generating a robust scan design in a system. The system is modeled selectively at a register-transfer level (RTL) or a gate level; the design includes at least a sequential element or a scan cell for mapping to a robust scan cell of a select robust scan cell type. The method comprises performing a scan replacement and a scan stitching on the design database based on a given control information file for synthesizing the robust scan cell on the design database; and generating the synthesized robust scan design at a pre-determined RTL or a pre-determined gate level.

Abstract: A method for providing ordered capture clocks to detect or locate faults within N clock domains and faults crossing any two clock domains in an integrated circuit or circuit assembly in scan-test or self-test mode, where N>1, each clock domain having one capture clock and a plurality of scan cells, each capture clock comprising a plurality of capture clock pulses; said method comprising: (a) generating and shifting-in N test stimuli to all said scan cells within said N clock domains in said integrated circuit or circuit assembly during a shift-in operation; (b) applying an ordered sequence of capture clocks to all said scan cells within said N clock domains, the ordered sequence of capture clocks comprising at least a plurality of capture clock pulses from two or more selected capture clocks placed in a sequential order such that all clock domains are never triggered simultaneously during a capture operation; and (c) analyzing output responses of all said scan cells to locate any faults therein.

Abstract: A low-pin-count scan compression method and apparatus for reducing test data volume and test application time in a scan-based integrated circuit. The scan-based integrated circuit contains one or more scan chains, each scan chain comprising one or more scan cells coupled in series. The method and apparatus includes a programmable pipelined decompressor comprising one or more shift registers, a combinational logic network, and an optional scan connector. The programmable pipelined decompressor decompresses a compressed scan pattern on its compressed scan inputs and drives the generated decompressed scan pattern at the output of the programmable pipelined decompressor to the scan data inputs of the scan-based integrated circuit. Any input constraints imposed by said combinational logic network are incorporated into an automatic test pattern generation (ATPG) program for generating the compressed scan pattern for one or more selected faults in one-step.

Abstract: A low-pin-count scan compression method and apparatus for reducing test data volume and test application time in a scan-based integrated circuit. The scan-based integrated circuit contains one or more scan chains, each scan chain comprising one or more scan cells coupled in series. The method and apparatus includes a programmable pipelined decompressor comprising one or more shift registers, a combinational logic network, and an optional scan connector. The programmable pipelined decompressor decompresses a compressed scan pattern on its compressed scan inputs and drives the generated decompressed scan pattern at the output of the programmable pipelined decompressor to the scan data inputs of the scan-based integrated circuit. Any input constraints imposed by said combinational logic network are incorporated into an automatic test pattern generation (ATPG) program for generating the compressed scan pattern for one or more selected faults in one-step.

Abstract: A pipelined scan compression method and apparatus for reducing test data volume and test application time in a scan-based integrated circuit without reducing the speed of the scan chain operation in scan-test mode or self-test mode. The scan-based integrated circuit contains one or more scan chains, each scan chain comprising one or more scan cells coupled in series. The method and apparatus includes a decompressor comprising one or more shift registers, a combinational logic network, and an optional scan connector. The decompressor decompresses a compressed scan pattern on its compressed scan inputs and drives the generated decompressed scan pattern at the output of the decompressor to the scan data inputs of the scan-based integrated circuit. Any input constraints imposed by said combinational logic network are incorporated into an automatic test pattern generation (ATPG) program for generating the compressed scan pattern for one or more selected faults in one-step.

Abstract: A low-pin-count scan compression method and apparatus for reducing test data volume and test application time in a scan-based integrated circuit. The scan-based integrated circuit contains one or more scan chains, each scan chain comprising one or more scan cells coupled in series. The method and apparatus includes a programmable pipelined decompressor comprising one or more shift registers, a combinational logic network, and an optional scan connector. The programmable pipelined decompressor decompresses a compressed scan pattern on its compressed scan inputs and drives the generated decompressed scan pattern at the output of the programmable pipelined decompressor to the scan data inputs of the scan-based integrated circuit. Any input constraints imposed by said_combinational logic network are incorporated into an automatic test pattern generation (ATPG) program for generating the compressed scan pattern for one or more selected faults in one-step.

Abstract: An apparatus and method for soft-error resilience or correction with the ability to perform a manufacturing test operation, a slow-speed snapshot operation, a slow-speed signature analysis operation, an at-speed signature analysis operation, a defect tolerance operation, or any combination of the above operations. In one embodiment, an apparatus includes a system circuit, a shadow circuit, and an output joining circuit for soft-error resilience. The output joining circuit coupled to the output terminals of the system circuit and the shadow circuit includes at least an S-element for defect tolerance. In another embodiment, an apparatus includes a system circuit, a shadow circuit, a debug circuit, and an output joining circuit for soft-error correction. The output joining circuit coupled to the output terminals of the system circuit, the shadow circuit, and the debug circuit includes at least a V-element for defect tolerance.