Patents by Inventor Zhi-Jie Wang

Zhi-Jie Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9481020
    Abstract: Bending members having slanted faces to engage folded edge portions of a housing panel, wherein the relative sliding movement between the folded edge portions and the bending members cause bending of each of the folded edge portions to an inwardly slanted angle.
    Type: Grant
    Filed: January 29, 2013
    Date of Patent: November 1, 2016
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Zhi-Jie Wang, Ming-Jen Yu, Tung-Yang Hu, Kevin L. Massaro, Chun-Pu Chen, Dimitre D. Mehandjiysky
  • Patent number: 8138584
    Abstract: An electromagnetic interference (EMI) and/or electromagnetic radiation shield is formed by forming a conductive layer (34, 46) over an encapsulant (32). The conductive layer includes a combination of a conductive glue (38, 48, 52) and a metal paint (36, 50). A wire loop (30) is coupled to the conductive layer and a leadframe (10).
    Type: Grant
    Filed: September 14, 2005
    Date of Patent: March 20, 2012
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Zhi-jie Wang, Jian-yong Liu
  • Publication number: 20090184403
    Abstract: An electromagnetic interference (EMI) and/or electromagnetic radiation shield is formed by forming a conductive layer (34, 46) over an encapsulant (32). The conductive layer includes a combination of a conductive glue (38, 48, 52) and a metal paint (36, 50). A wire loop (30) is coupled to the conductive layer and a leadframe (10).
    Type: Application
    Filed: September 14, 2005
    Publication date: July 23, 2009
    Applicant: FREESCALE SEMICONDUCTOR. INC.
    Inventors: Zhi-Jie Wang, Jian-Yong Liu
  • Publication number: 20080290487
    Abstract: A lead frame for a semiconductor device includes at least one row of contact terminals and a die pad for receiving an integrated circuit die. An isolation material is located between the contact terminals and the die pad. The isolation material electrically isolates adjacent lead fingers from each other and from the die pad. The isolation material also holds the lead fingers in place during a wire bonding operation and thus the bottom of the lead frame does not have to be taped during the assembly process, which saves taping and detaping steps from being performed. The isolation material also prevents resin bleed problems that sometimes occur when using tape. If a sawing step is performed, the saw need only cut through the isolation material instead of a metal, and thus saw blade life is improved.
    Type: Application
    Filed: April 8, 2008
    Publication date: November 27, 2008
    Applicant: FREESCALE SEMICONDUCTOR, INC.
    Inventors: Li-Guo ZHAO, Zhe Li, Zhi-Jie Wang, Guo-Ping Lu
  • Publication number: 20080283980
    Abstract: A lead frame (10) for a quad flat non-leaded semiconductor package (606), includes a tie bar (12), a first group of leads (22) extending a first length from the tie bar (12) in a transverse direction (Y), and a second group of leads (24) extending a second length from the tie bar (12) in the transverse direction (Y). The second length is greater than the first length, and leads from the first and second group of leads (22, 24) alternate in a longitudinal direction (X) along the tie bar (12) so that the first and second groups of leads are staggered. The second group of leads (24) is displaced from the first group of leads (22) in a Z-direction (Z) perpendicular to both the transverse (Y) and longitudinal (X) directions. The leads of the first and second groups of leads (22, 24) each have a respective contact terminal (26 and 28) at their distal ends. The contact terminals (26 and 28) each have a contact face (40 and 42) in a contact plane (44).
    Type: Application
    Filed: April 9, 2008
    Publication date: November 20, 2008
    Applicant: FREESCALE SEMICONDUCTOR, INC
    Inventors: Wei Gao, Zhi-Gang Bai, Li-Wei Liu, Zhi-Jie Wang, Yuan Zang, Hong Zhu
  • Publication number: 20060038266
    Abstract: A semiconductor device (20) includes an integrated circuit (22) having a plurality of bonding pads (24) located on a peripheral portion of its top surface and a groove (26) formed in its bottom surface (28). The groove (26) extends from one end to an opposite end of the IC (22). Lead fingers (30) that surround the IC (22) are electrically connected to respective ones of the bonding pads (24) via wirebonding. A mold compound (34) covers the top surfaces of the IC (22) and the lead fingers (30), and the electrical connections. At least the bottom surfaces of the lead fingers (30) and the IC (22) are exposed, except for the groove (26), which is filled with the mold compound (34).
    Type: Application
    Filed: September 30, 2004
    Publication date: February 23, 2006
    Inventors: Fu-Bin Song, Yan-Feng Liu, Zhi-Jie Wang
  • Patent number: 6727112
    Abstract: A method of manufacturing a semiconductor optical device comprising the steps of: providing a substrate having an active layer thereon; providing an aluminium-bearing layer, the aluminium bearing layer being adjacent the active layer; and oxidising the aluminium-bearing layer substantially entirely.
    Type: Grant
    Filed: August 16, 2001
    Date of Patent: April 27, 2004
    Assignee: Agency for Science, Technology and Research
    Inventors: Zhi-Jie Wang, Soo-Jin Chua, Fan Zhou, Wei Wang
  • Publication number: 20020074600
    Abstract: A method of manufacturing a semiconductor optical device comprising the steps of: providing a substrate having an active layer thereon; providing an aluminium-bearing layer, the aluminium bearing, layer being adjacent the active layer; and oxidising the aluminium-bearing layer substantially entirely.
    Type: Application
    Filed: August 16, 2001
    Publication date: June 20, 2002
    Inventors: Zhi-Jie Wang, Soo-Jin Chua, Fan Zhou, Wei Wang