Patents by Inventor Zhi-Min Ling

Zhi-Min Ling has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5963780
    Abstract: An apparatus and method for detecting defect sizes in polysilicon and source-drain semiconductor devices and methods for making the same. Implemented is a double bridge test structure that includes a resistor path of first semiconductor material, such as doped silicon comprising a plurality of strip segments and with interconnection segments. A plurality of strips of second semiconductor material having a substantially lower resistivity are connected to form parallel circuit interconnections with the corresponding strip segments. The test structure is formed by masking techniques wherein a prescribed mask region enables portions of the silicon resistor or deposited polysilicon to be selectively silicided to form silicide and polycide, respectively. One embodiment for testing for defects in a polysilicon layer uses polycide as the low-resistivity strips, enabling the testing of open and short-circuit defects.
    Type: Grant
    Filed: July 24, 1997
    Date of Patent: October 5, 1999
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Zhi-Min Ling, Yung-Tao Lin, Ying Shiau
  • Patent number: 5930138
    Abstract: An arrangement and method for detecting sequential processing effects on products to be manufactured in a manufacturing process orders a first set of the products in a first specified processing sequence for a first process step in the manufacturing process. In order to prevent any positional trend created at one process step from being carried over into the next process step, the first set of the products is re-ordered into a second, different specified processing sequence for a second process step in the manufacturing process. Data regarding responses of the first set of the products to the process steps are extracted. The extracted data are correlated with the first and second processing sequences and data analysis is performed on the correlated extracted data.
    Type: Grant
    Filed: September 10, 1997
    Date of Patent: July 27, 1999
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Yung-Tao Lin, Zhi-Min Ling, James Pak, Ying Shiau
  • Patent number: 5821765
    Abstract: An apparatus and method for detecting defect sizes in polysilicon and source-drain semiconductor devices and methods for making the same. Implemented is a double bridge test structure that includes a resistor path of first semiconductor material, such as doped silicon comprising a plurality of strip segments and with interconnection segments. A plurality of strips of second semiconductor material having a substantially lower resistivity are connected to form parallel circuit interconnections with the corresponding strip segments. The test structure is formed by masking techniques wherein a prescribed mask region enables portions of the silicon resistor or deposited polysilicon to be selectively silicided to form silicide and polycide, respectively. One embodiment for testing for defects in a polysilicon layer uses polycide as the low-resistivity strips, enabling the testing of open and short-circuit defects.
    Type: Grant
    Filed: July 24, 1997
    Date of Patent: October 13, 1998
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Zhi-Min Ling, Yung-Tao Lin, Ying Shiau
  • Patent number: 5761065
    Abstract: An arrangement and method for detecting sequential processing effects on devices to be manufactured in a manufacturing process extracts data regarding responses of the devices to a process step in the manufacturing process and data regarding a processing sequence of the devices in that process step. The extracted data is refined before analysis and control chart rules are then applied to the refined data. These control chart rules detect whether there are any unusual processing effects caused by the sequence of processing of the devices in any one of the individual processing steps. Application of control chart rules to the refined data allows an automatic determination of whether there are any rule violations. One or more control charts which have a rule violation are automatically generated when it is determined that there is a rule violation. Process engineers may then use the automatically generated charts to direct their efforts at improving the manufacturing process.
    Type: Grant
    Filed: March 30, 1995
    Date of Patent: June 2, 1998
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Richard Charles Kittler, Zhi-Min Ling, James Minsu Pak, Yung-Tao Lin, Ying Shiau
  • Patent number: 5716856
    Abstract: An arrangement and method for detecting sequential processing effects on products to be manufactured in a manufacturing process orders a first set of the products in a first specified processing sequence for a first process step in the manufacturing process. In order to prevent any positional trend created at one process step from being carried over into the next process step, the first set of the products is re-ordered into a second, different specified processing sequence for a second process step in the manufacturing process. Data regarding responses of the first set of the products to the process steps are extracted. The extracted data are correlated with the first and second processing sequences and data analysis is performed on the correlated extracted data.
    Type: Grant
    Filed: August 22, 1995
    Date of Patent: February 10, 1998
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Yung-Tao Lin, Zhi-Min Ling, James Pak, Ying Shiau
  • Patent number: 5670891
    Abstract: An apparatus and method for detecting defect sizes in polysilicon and source-drain semiconductor devices and methods for making the same. Implemented is a double bridge test structure that includes a resistor path of first semiconductor material, such as doped silicon comprising a plurality of strip segments and with interconnection segments. A plurality of strips of second semiconductor material having a substantially lower resistivity are connected to form parallel circuit interconnections with the corresponding strip segments. The test structure is formed by masking techniques wherein a prescribed mask region enables portions of the silicon resistor or deposited polysilicon to be selectively silicided to form silicide and polycide, respectively. One embodiment for testing for defects in a polysilicon layer uses polycide as the low-resistivity strips, enabling the testing of open and short-circuit defects.
    Type: Grant
    Filed: June 7, 1995
    Date of Patent: September 23, 1997
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Zhi-Min Ling, Yung-Tao Lin, Ying Shiau
  • Patent number: 5598341
    Abstract: A real-time in-line defect disposition and yield forecasting system for a semiconductor wafer having layer containing devices includes an in-line fabrication inspection tool, a design review station, and a yield management station. The in-line fabrication inspection tool inspects at least two layers of the semiconductor wafer and produces first information including particle size, particle location and number of particles introduced therein for each of these layers. The design review station inspects the layers of the semiconductor wafer and produces second information including layouts of each of the layers. The yield management station is operatively connected to the in-line fabrication inspection tool and to the design review station. The yield management station retrieves the first information and the second information from the in-line fabrication inspection tool and from the design review station.
    Type: Grant
    Filed: March 10, 1995
    Date of Patent: January 28, 1997
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Zhi-Min Ling, Thao Vo, Siu-May Ho, Ying Shiau, Yeng-Kaung Peng, Yung-Tao Lin