Patents by Inventor Zhi Ning

Zhi Ning has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240194758
    Abstract: A method for forming a gate all around transistor includes forming a plurality of semiconductor nanosheets. The method includes forming a cladding inner spacer between a source region of the transistor and a gate region of the transistor. The method includes forming sheet inner spacers between the semiconductor nanosheets in a separate deposition process from the cladding inner spacer.
    Type: Application
    Filed: February 22, 2024
    Publication date: June 13, 2024
    Inventors: Zhi-Chang LIN, Kuan-Ting PAN, Shih-Cheng CHEN, Jung-Hung CHANG, Lo-Heng CHANG, Chien-Ning YAO, Kuo-Cheng CHIANG
  • Patent number: 11996482
    Abstract: A device includes a semiconductor substrate, a channel layer, a gate structure, source/drain epitaxial structures, and a dielectric isolation layer. The channel layer is over the semiconductor substrate. The gate structure is over the semiconductor substrate and surrounds the channel layer. The source/drain epitaxial structures are connected to the channel layer and arranged in a first direction. The dielectric isolation layer is between the gate structure and the semiconductor substrate. The dielectric isolation layer is wider than the gate structure but narrower than the channel layer in the first direction.
    Type: Grant
    Filed: March 13, 2023
    Date of Patent: May 28, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Zhi-Chang Lin, Shih-Cheng Chen, Jung-Hung Chang, Lo-Heng Chang, Chien-Ning Yao
  • Publication number: 20240170556
    Abstract: A method for forming a semiconductor structure is provided. The method includes forming a spacer layer along a first fin structure and a second fin structure, etching a first portion of the spacer layer and the first fin structure to form first fin spacers and a first recess between the first fin spacers, etching a second portion of the spacer layer and the second fin structure to form second fin spacers and a second recess between the second fin spacers, and forming a first source/drain feature in the first recess and a second source/drain feature in the second recess. The second fin structure is wider than the first fin structure. The first fin spacers have a first height, and the second fin spacers have a second height that is greater than the first height.
    Type: Application
    Filed: February 20, 2023
    Publication date: May 23, 2024
    Inventors: Shih-Cheng CHEN, Zhi-Chang LIN, Jung-Hung CHANG, Chien-Ning YAO, Tsung-Han CHUANG, Kuo-Cheng CHIANG
  • Publication number: 20240170534
    Abstract: A method for manufacturing a nanosheet semiconductor device includes: forming a liner layer to cover first and second fin structures, each of the fin structures including a stacked structure, a poly gate disposed on the stacked structure, and inner spacers, the stacked structure including sacrificial features covered by the inner spacers, and channel features disposed to alternate with the sacrificial features; forming a dielectric layer to cover the liner layer, the dielectric layer including an upper portion, a lower portion, and an interconnecting portion that interconnects the upper and lower portions and that laterally covers the liner layer; subjecting the upper and lower portions to a directional treatment; and removing the upper and interconnecting portions of the dielectric layer and a portion of the liner layer, to form a liner and a bottom dielectric insulator disposed on the liner.
    Type: Application
    Filed: February 23, 2023
    Publication date: May 23, 2024
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Zhi-Chang LIN, Ko-Feng CHEN, Chien-Ning YAO, Chien-Hung LIN
  • Publication number: 20240170337
    Abstract: The present disclosure describes a semiconductor structure with a dielectric liner. The semiconductor structure includes a substrate and a fin structure on the substrate. The fin structure includes a stacked fin structure, a fin bottom portion below the stacked fin structure, and an isolation layer between the stacked fin structure and the bottom fin portion. The semiconductor structure further includes a dielectric liner in contact with an end of the stacked fin structure and a spacer structure in contact with the dielectric liner.
    Type: Application
    Filed: January 30, 2024
    Publication date: May 23, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company Ltd.
    Inventors: Zhi-Chang LIN, Shih-Cheng CHEN, Kuo-Cheng CHIANG, Kuan-Ting PAN, Jung-Hung CHANG, Lo-Heng CHANG, Chien Ning YAO
  • Publication number: 20240153958
    Abstract: A semiconductor device structure, along with methods of forming such, are described. The structure includes a plurality of semiconductor layers having a first group of semiconductor layers, a second group of semiconductor layers disposed over and aligned with the first group of semiconductor layers, and a third group of semiconductor layers disposed over and aligned with the second group of semiconductor layers. The structure further includes a first source/drain epitaxial feature in contact with a first number of semiconductor layers of the first group of semiconductor layers and a second source/drain epitaxial feature in contact with a second number of semiconductor layers of the third group of semiconductor layers. The first number of semiconductor layers of the first group of semiconductor layers is different from the second number of semiconductor layers of the third group of semiconductor layers.
    Type: Application
    Filed: January 7, 2024
    Publication date: May 9, 2024
    Inventors: Jung-Hung CHANG, Zhi-Chang LIN, Shih-Cheng CHEN, Chien Ning YAO, Kuo-Cheng CHIANG, Chih-Hao WANG
  • Patent number: 11967594
    Abstract: A semiconductor device structure, along with methods of forming such, are described. The structure includes a stack of semiconductor layers spaced apart from and aligned with each other, a first source/drain epitaxial feature in contact with a first one or more semiconductor layers of the stack of semiconductor layers, and a second source/drain epitaxial feature disposed over the first source/drain epitaxial feature. The second source/drain epitaxial feature is in contact with a second one or more semiconductor layers of the stack of semiconductor layers. The structure further includes a first dielectric material disposed between the first source/drain epitaxial feature and the second source/drain epitaxial feature and a first liner disposed between the first source/drain epitaxial feature and the second source/drain epitaxial feature. The first liner is in contact with the first source/drain epitaxial feature and the first dielectric material.
    Type: Grant
    Filed: August 10, 2022
    Date of Patent: April 23, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Shih-Cheng Chen, Zhi-Chang Lin, Jung-Hung Chang, Lo Heng Chang, Chien Ning Yao, Kuo-Cheng Chiang, Chih-Hao Wang
  • Publication number: 20240112959
    Abstract: A method of fabricating a device includes forming a dummy gate over a plurality of fins. Thereafter, a first portion of the dummy gate is removed to form a first trench that exposes a first hybrid fin and a first part of a second hybrid fin. The method further includes filling the first trench with a dielectric material disposed over the first hybrid fin and over the first part of the second hybrid fin. Thereafter, a second portion of the dummy gate is removed to form a second trench and the second trench is filled with a metal layer. The method further includes etching-back the metal layer, where a first plane defined by a first top surface of the metal layer is disposed beneath a second plane defined by a second top surface of a second part of the second hybrid fin after the etching-back the metal layer.
    Type: Application
    Filed: December 1, 2023
    Publication date: April 4, 2024
    Inventors: Kuan-Ting PAN, Zhi-Chang LIN, Yi-Ruei JHAN, Chi-Hao WANG, Huan-Chieh SU, Shi Ning JU, Kuo-Cheng CHIANG
  • Publication number: 20240096895
    Abstract: According to one example, a semiconductor device includes a substrate and a fin stack that includes a plurality of nanostructures, a gate device surrounding each of the nanostructures, and inner spacers along the gate device and between the nanostructures. A width of the inner spacers differs between different layers of the fin stack.
    Type: Application
    Filed: November 29, 2023
    Publication date: March 21, 2024
    Inventors: Jui-Chien Huang, Shih-Cheng Chen, Chih-Hao Wang, Kuo-Cheng Chiang, Zhi-Chang Lin, Jung-Hung Chang, Lo-Heng Chang, Shi Ning Ju, Guan-Lin Chen
  • Patent number: 11929287
    Abstract: The present disclosure describes a semiconductor structure with a dielectric liner. The semiconductor structure includes a substrate and a fin structure on the substrate. The fin structure includes a stacked fin structure, a fin bottom portion below the stacked fin structure, and an isolation layer between the stacked fin structure and the bottom fin portion. The semiconductor structure further includes a dielectric liner in contact with an end of the stacked fin structure and a spacer structure in contact with the dielectric liner.
    Type: Grant
    Filed: April 23, 2021
    Date of Patent: March 12, 2024
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Zhi-Chang Lin, Shih-Cheng Chen, Kuo-Cheng Chiang, Kuan-Ting Pan, Jung-Hung Chang, Lo-Heng Chang, Chien Ning Yao
  • Patent number: 11916122
    Abstract: A method for forming a gate all around transistor includes forming a plurality of semiconductor nanosheets. The method includes forming a cladding inner spacer between a source region of the transistor and a gate region of the transistor. The method includes forming sheet inner spacers between the semiconductor nanosheets in a separate deposition process from the cladding inner spacer.
    Type: Grant
    Filed: July 8, 2021
    Date of Patent: February 27, 2024
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Zhi-Chang Lin, Kuan-Ting Pan, Shih-Cheng Chen, Jung-Hung Chang, Lo-Heng Chang, Chien-Ning Yao, Kuo-Cheng Chiang
  • Patent number: 11460434
    Abstract: The invention provides a gas detection system and a method with eliminating influence of ambient temperature and humidity change, the gas detection system comprises a bare sensor, a reference sensor and a calculation module; the bare sensor is used to detect a target gas in an ambient gas to obtain a first feedback signal; the reference sensor is used to selectively isolate the target gas in the ambient gas to produce a zero gas and to detect the zero gas to obtain a second feedback signal, the calculation module is used to calculate a difference between the first feedback signal and the second feedback signal to obtain a third feedback signal, and to obtain a target gas concentration by calculating the third feedback signal according to a calibration formula. The invention improves the measurement accuracy to the target gas concentration, which are efficient and reliable and have good technical effects.
    Type: Grant
    Filed: May 29, 2019
    Date of Patent: October 4, 2022
    Assignee: SAPIENS ENVIRONMENTAL TECHNOLOGY CO., LTD.
    Inventors: Ying Wang, Li Sun, Qing Zhang, Zhi Ning
  • Publication number: 20210310986
    Abstract: The invention provides a gas detection system and a method with eliminating influence of ambient temperature and humidity change, the gas detection system comprises a bare sensor, a reference sensor and a calculation module; the bare sensor is used to detect a target gas in an ambient gas to obtain a first feedback signal; the reference sensor is used to selectively isolate the target gas in the ambient gas to produce a zero gas and to detect the zero gas to obtain a second feedback signal, the calculation module is used to calculate a difference between the first feedback signal and the second feedback signal to obtain a third feedback signal, and to obtain a target gas concentration by calculating the third feedback signal according to a calibration formula. The invention improves the measurement accuracy to the target gas concentration, which are efficient and reliable and have good technical effects.
    Type: Application
    Filed: May 29, 2019
    Publication date: October 7, 2021
    Inventors: Ying Wang, Li Sun, Qing Zhang, Zhi Ning
  • Patent number: 10504120
    Abstract: Determining a temporary transaction limit is disclosed, including: receiving a transaction request message, wherein the transaction request message includes a total transaction cost and identifying information associated with a user; determining that the total transaction cost is greater than a predetermined limit; retrieving historical transaction data associated with a plurality of users; determining a plurality of clustered classifications from the historical transaction data associated with the plurality of users; determining a clustered classification from the plurality of clustered classifications based on historical transaction data associated with the user; determining a dynamic quota corresponding to the clustered classification for the user using a predetermined mapping rule; and determining whether the transaction request message is approved based on comparing the total transaction cost to a temporary transaction limit, wherein the temporary transaction limit comprises a combination of the predeter
    Type: Grant
    Filed: March 12, 2015
    Date of Patent: December 10, 2019
    Assignee: Alibaba Group Holding Limited
    Inventors: Yun Yue, Ji Huang, Zhi Ning
  • Patent number: 10113999
    Abstract: A device for detecting a substance includes a light source arranged to emit a light signal through a sample cell, wherein the sample cell is arranged to temporally house a sample compound having a portion of the substance, and an optical processing module arranged to detect the light signal emitted through the sample cell to identify physical attributes of the light signal altered by the sample compound, wherein the physical attributes of the light signal altered by the sample compound is processed so as to detect the substance within the sample compound.
    Type: Grant
    Filed: June 16, 2014
    Date of Patent: October 30, 2018
    Assignee: CITY UNIVERSITY OF HONG KONG
    Inventors: Zhi Ning, Ka Lok Chan, Dane Westerdahl, Ka Chun Wong
  • Patent number: 9503480
    Abstract: Deploying policy configuration across multiple security devices through hierarchical configuration templates is disclosed. In some embodiments, deploying policy configuration across multiple security devices through hierarchical configuration templates for configuring a plurality of security devices includes receiving at a first security device a hierarchy of templates from a central management server, in which the hierarchy of templates includes configuration information for a group of security devices, and in which the first security device is included in the group of security devices; and reconciling on the first security device's configuration information included in the hierarchy of templates and device specific configuration based on local configuration information, in which the first security device performs an object level reconciliation to maintain device configuration consistency.
    Type: Grant
    Filed: March 31, 2015
    Date of Patent: November 22, 2016
    Assignee: Palo Alto Networks, Inc.
    Inventors: Anupam Bharali, Kunal Kundu, Zhi Ning Wang
  • Publication number: 20150278813
    Abstract: Determining a temporary transaction limit is disclosed, including: receiving a transaction request message, wherein the transaction request message includes a total transaction cost and identifying information associated with a user; determining that the total transaction cost is greater than a predetermined limit; retrieving historical transaction data associated with a plurality of users; determining a plurality of clustered classifications from the historical transaction data associated with the plurality of users; determining a clustered classification from the plurality of clustered classifications based on historical transaction data associated with the user; determining a dynamic quota corresponding to the clustered classification for the user using a predetermined mapping rule; and determining whether the transaction request message is approved based on comparing the total transaction cost to a temporary transaction limit, wherein the temporary transaction limit comprises a combination of the predeter
    Type: Application
    Filed: March 12, 2015
    Publication date: October 1, 2015
    Inventors: Yun Yue, Ji Huang, Zhi Ning
  • Publication number: 20150281285
    Abstract: Deploying policy configuration across multiple security devices through hierarchical configuration templates is disclosed. In some embodiments, deploying policy configuration across multiple security devices through hierarchical configuration templates for configuring a plurality of security devices includes receiving at a first security device a hierarchy of templates from a central management server, in which the hierarchy of templates includes configuration information for a group of security devices, and in which the first security device is included in the group of security devices; and reconciling on the first security device's configuration information included in the hierarchy of templates and device specific configuration based on local configuration information, in which the first security device performs an object level reconciliation to maintain device configuration consistency.
    Type: Application
    Filed: March 31, 2015
    Publication date: October 1, 2015
    Inventors: Anupam Bharali, Kunal Kundu, Zhi Ning Wang
  • Publication number: 20150253297
    Abstract: A device for detecting a substance includes a light source arranged to emit a light signal through a sample cell, wherein the sample cell is arranged to temporally house a sample compound having a portion of the substance, and an optical processing module arranged to detect the light signal emitted through the sample cell to identify physical attributes of the light signal altered by the sample compound, wherein the physical attributes of the light signal altered by the sample compound is processed so as to detect the substance within the sample compound.
    Type: Application
    Filed: June 16, 2014
    Publication date: September 10, 2015
    Inventors: Zhi Ning, Ka Lok Chan, Dane Westerdahl, Ka Chun Wong
  • Patent number: 9027077
    Abstract: Deploying policy configuration across multiple security devices through hierarchical configuration templates is disclosed. In some embodiments, deploying policy configuration across multiple security devices through hierarchical configuration templates for configuring a plurality of security devices includes receiving at a first security device a hierarchy of templates from a central management server, in which the hierarchy of templates includes configuration information for a group of security devices, and in which the first security device is included in the group of security devices; and reconciling on the first security device's configuration information included in the hierarchy of templates and device specific configuration based on local configuration information, in which the first security device performs an object level reconciliation to maintain device configuration consistency.
    Type: Grant
    Filed: April 30, 2012
    Date of Patent: May 5, 2015
    Assignee: Palo Alto Networks, Inc.
    Inventors: Anupam Bharali, Kunal Kundu, Zhi Ning Wang