Abstract: A swirl-type demulsification and dehydration device for oil-water emulsions, including a swirler. An open end of a swirl chamber of the swirler faces towards an underflow pipe and communicates with the underflow pipe through a composite curved pipe section coaxial with the swirl chamber. A large-diameter end of a concave arc transition section is connected to the open end of the swirl chamber, is the same with the swirl chamber in inner diameter. A large-diameter end of a straight cone transition section is tangent to a small-diameter end of the concave arc transition section. A small-diameter end of the straight cone transition section is tangent to a large-diameter end of a convex elliptical arc transition section. A small-diameter end of the convex elliptical arc transition section is connected to the underflow pipe.

Abstract: An antenna and a terminal device include a Printed Circuit Board (PCB), a first main antenna, a second main antenna and a connection component. The first main antenna is printed on the PCB, and the second main antenna is configured outside the PCB and electrically connected to the first main antenna through the connection component. By connecting the antenna printed on the PCB with the antenna configured outside the PCB, the limitation that wiring space is not enough in the existing antenna design is made up, and the utilization of the limited space can be significantly improved when the wiring of the antenna is designed.

Abstract: An antenna and a terminal device include a Printed Circuit Board (PCB), a first main antenna, a second main antenna and a connection component. The first main antenna is printed on the PCB, and the second main antenna is configured outside the PCB and electrically connected to the first main antenna through the connection component. By connecting the antenna printed on the PCB with the antenna configured outside the PCB, the limitation that wiring space is not enough in the existing antenna design is made up, and the utilization of the limited space can be significantly improved when the wiring of the antenna is designed.

Abstract: A circuit for end-of-burst detection in a portion of a received bit stream is disclosed. The circuit comprises: a first counter for counting the number of bits in the portion, a second counter for counting the number of bit value transitions in the portion, and a circuit for comparing the counted number of bits in the portion and the counted number of bit value transitions therein with preset values, the circuit for comparing is further arranged for generating a signal indicative of end-of-burst detection based on the result of the comparison.

Abstract: Systems and methods for transferring incoming single-ended burst signals of which at least one characteristic varies widely from burst to burst onto a pair of differential lines. The systems comprise an input for receiving an incoming burst signal, a signal adaptation block for adapting said widely varying characteristic and a single-ended-to-differential converter. In a first aspect a reset signal for resetting a settings determination block, which controls the signal adaptation block, is sent backwards over the differential lines, preferably using a common-mode signal. In a second aspect, a status freezing mechanism is employed for freezing the settings of the settings determination block after the end of the preamble of an incoming burst.

Abstract: Systems and methods for transferring incoming single-ended burst signals of which at least one characteristic varies widely from burst to burst onto a pair of differential lines. The systems comprise an input for receiving an incoming burst signal, a signal adaptation block for adapting said widely varying characteristic and a single-ended-to-differential converter. In a first aspect a reset signal for resetting a settings determination block, which controls the signal adaptation block, is sent backwards over the differential lines, preferably using a common-mode signal. In a second aspect, a status freezing mechanism is employed for freezing the settings of the settings determination block after the end of the preamble of an incoming burst.

Abstract: A circuit for end-of-burst detection in a portion of a received bit stream is disclosed. The circuit comprises: a first counter for counting the number of bits in the portion, a second counter for counting the number of bit value transitions in the portion, and a circuit for comparing the counted number of bits in the portion and the counted number of bit value transitions therein with preset values, the circuit for comparing is further arranged for generating a signal indicative of end-of-burst detection based on the result of the comparison.

Abstract: Systems and methods for transferring incoming single-ended burst signals of which at least one characteristic varies widely from burst to burst onto a pair of differential lines. The systems comprise an input for receiving an incoming burst signal, a signal adaptation block for adapting said widely varying characteristic and a single-ended-to-differential converter. In a first aspect a reset signal for resetting a settings determination block, which controls the signal adaptation block, is sent backwards over the differential lines, preferably using a common-mode signal. In a second aspect, a status freezing mechanism is employed for freezing the settings of the settings determination block after the end of the preamble of an incoming burst.

Abstract: The present invention is related to a circuit (1) for detecting activity in a burst-mode receiver. The circuit is arranged for receiving an input signal (2) comprising a preamble. The circuit comprises a differentiator (11) for detecting signal transitions in the input signal (2) whereby the preamble comprises information on operating said differentiator (11). In a preferred embodiment, the information is a time constant. The circuit further comprises an integrator (12) arranged for being fed with an output of the differentiator. The resulting signal is compared to a reference (16). If this reference is crossed, activity is detected. In an embodiment a front-end circuit is presented comprising next to a circuit for detecting activity, a reset circuit arranged for resetting the front-end circuit and a clock phase alignment circuit arranged for recovering the phase.

Abstract: A FFT/IFFT processor and an intellectual property (IP) builder are disclosed. Which include a circuit applying the mixed-radix algorithm and a parametric graphic user interface (GUI). The circuit is for a parametric IP builder. The parametric GUI is for user to complete hardware design and functional test of FFT/IFFT processor by software. The IP builder could accelerate the progress of processor design and SOC integration.

Abstract: One inventive aspect relates to an emulation system for real-time simulation of the physical layer of an analog communication system based at least on partly digital computation. The emulation system comprises a digital portion configured to perform digital computations and represent at least part of the signal propagation in the communication system. The system further comprises an analog portion configured to perform analog signal processing and represent other aspects of the physical layer of the communication system. The analog portion provides inputs to and receives outputs from the digital portion. The digital portion is configured to digitally compensate for inaccuracies introduced by the analog portion. Methods of emulating communication systems are also provided.

Abstract: A laser transmitter comprising a laser diode (1) and a monitoring photodiode (2) adapted to receive a small part (LS1) of a light signal (LS) of the laser diode and to derive therefrom an output current (SC). The transmitter further comprises regulation means (4) adapted for receiving the output current and for sending a signal (CS) to a current driver (5) in order to regulate the input current (IC) of the laser diode (1) as a function of this output current (SC). The transmitter also comprises a register (6) adapted to store data to be used by the regulation means (4) or to be read by a serial interface, and pattern detection means (7) adapted to scan all the traffic and thus all the packets of the upstream flow to the laser diode (1) to check whether pre-determined bit-patterns are present.